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MOTOROLA
Order this document by MC68HC916X1TS/D
SEMICONDUCTOR
TECHNICAL DATA
MC68HC916X1
Technical Summary
16-Bit Modular Microcontroller
1 Introduction
The MC68HC916X1 microcontroller (MCU) is a high-speed 16-bit device that is upwardly code compatible with M68HC11 controllers. It is a member of the M68300/68HC16 Family of modular microcontrollers. M68HC16 controllers are built up from standard modules that interface via a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applications. The MC68HC916X1 incorporates a true 16-bit CPU (CPU16), a single-chip integration module (SCIM), an 8/10-bit analog-to-digital converter (ADC), a queued serial module (QSM), a generalpurpose timer (GPT), 2 Kbytes of standby RAM (SRAM), 48 Kbytes of flash EEPROM (FLASH), and 2 Kbytes of block-erasable flash EEPROM (BEFLASH). These modules are interconnected by the intermodule bus (IMB). The maximum system clock for the MC68HC916X1 is 16.78 MHz. A phase-locked loop circuit synthesizes the clock from a frequency reference. Either a crystal with a nominal frequency of 4.194 MHz or an externally generated signal can be used. System hardware and software support changes in the clock rate during operation. Because the MC68HC916X1 is a fully static design, register and memory contents are not affected by clock rate changes. High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power consumption of the MC68HC916X1 low. Power consumption can be minimized by stopping the system clock. The M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability.
Table 1 Ordering Information
Package Type 120 QFP Frequency 16.78 MHz Temperature - 40 to + 85 C Package Order Quantity 250 50 2 Order Number MC916X1CTH16B1 MC68HC916X1CTH16 SPMC916X1CTH16
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) MOTOROLA INC., 1996
M
TABLE OF CONTENTS
Section Page
1
1.1 1.2 1.3 1.4 1.5
Introduction
1 Features ......................................................................................................................................4 Block Diagram .............................................................................................................................5 Pin Assignments ..........................................................................................................................6 Address Map ...............................................................................................................................6 Intermodule Bus ..........................................................................................................................7
2
2.1 2.2 2.3 2.4 2.5
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11
4
4.1 4.2 4.3 4.4 4.5 4.6 4.7
5
5.1 5.2 5.3 5.4 5.5
6
6.1 6.2 6.3 6.4 6.5
7
7.1 7.2 7.3 7.4 7.5
Signal Descriptions 8 Pin Characteristics ......................................................................................................................8 MCU Power Connections ............................................................................................................9 MCU Output Driver Types ...........................................................................................................9 MCU Signal Characteristics ......................................................................................................10 MCU Signal Function ................................................................................................................11 Single-Chip Integration Module 13 Overview ...................................................................................................................................13 System Configuration ................................................................................................................15 System Clock ............................................................................................................................20 System Protection .....................................................................................................................25 External Bus Interface ...............................................................................................................28 Bus Control Signals ...................................................................................................................29 Resets .......................................................................................................................................32 Interrupts ...................................................................................................................................34 Chip Selects ..............................................................................................................................37 General-Purpose Input/Output ..................................................................................................45 Factory Test ..............................................................................................................................50 Central Processing Unit 51 Overview ...................................................................................................................................51 M68HC11 Compatibility .............................................................................................................51 Programming Model ..................................................................................................................52 Data Types ................................................................................................................................53 Addressing Modes .....................................................................................................................54 Instruction Set ...........................................................................................................................55 Exceptions .................................................................................................................................75 Analog-to-Digital Converter Module 78 Analog Subsystem ....................................................................................................................78 Digital Control Subsystem .........................................................................................................78 Bus Interface Subsystem ..........................................................................................................78 ADC Address Map .....................................................................................................................80 ADC Registers ...........................................................................................................................81 General-Purpose Timer Module 87 Overview ...................................................................................................................................87 GPT Address Map .....................................................................................................................88 Capture/Compare Unit ..............................................................................................................88 Pulse-Width Modulator ..............................................................................................................91 GPT Registers ...........................................................................................................................93 Queued Serial Module 100 Overview .................................................................................................................................100 Pin Function ............................................................................................................................101 QSM Registers ........................................................................................................................102 QSPI Submodule .....................................................................................................................105 SCI Submodule .......................................................................................................................114 Standby RAM Module 120 Overview .................................................................................................................................120 SRAM Register Block ..............................................................................................................120 SRAM Registers ......................................................................................................................120 SRAM Operation .....................................................................................................................122
8
8.1 8.2 8.3 8.4
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MC68HC916X1 MC68HC916X1TS/D
TABLE OF CONTENTS (Continued)
Section Page
9
9.1 9.2 9.3 9.4 9.5 9.6
10
10.1 10.2 10.3 10.4 10.5
11
Flash EEPROM Module 123 Overview .................................................................................................................................123 Address Map ...........................................................................................................................123 Flash EEPROM Control Block .................................................................................................124 Flash EEPROM Array .............................................................................................................125 Flash EEPROM Registers .......................................................................................................125 Flash EEPROM Operation ......................................................................................................128 Block-Erasable Flash EEPROM 133 Overview .................................................................................................................................133 BEFLASH Control Block ..........................................................................................................134 BEFLASH Array ......................................................................................................................134 BEFLASH Registers ................................................................................................................134 BEFLASH Operation ...............................................................................................................137 Electrical Characteristics 140
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1.1 Features * CPU16 -- 16-bit architecture -- Full set of 16-bit instructions -- Three 16-bit index registers -- Two 16-bit accumulators -- 16-bit multiply and accumulate (digital signal processing support) -- High-level language support -- Fast interrupt response time -- Hardware breakpoint signal/Background debugging mode -- Fully static implementation * Single-Chip Integration Module (SCIM) -- Single-chip or expanded modes of operation -- External bus support in expanded mode -- Five programmable chip-select outputs -- Watchdog timer, clock monitor, and bus monitor -- Address and data bus provide 33 discrete I/O lines in single-chip mode -- Phase-locked loop (PLL) clock system * 8/10-Bit Analog-to-Digital Converter (ADC) -- Six channels, eight result registers -- Eight automated modes -- Three result alignment formats * Queued Serial Module (QSM) -- Enhanced serial communication interface (SCI) -- Queued serial peripheral interface (QSPI) -- Dual function I/O ports * General-Purpose Timer (GPT) -- Two 16-bit free-running counters with prescaler -- Three input capture channels -- Four output compare channels -- One input capture/output compare channel -- One pulse accumulator/event counter input -- Two pulse-width modulation outputs -- Optional external clock input * 2 Kbyte Standby RAM Module (SRAM) -- External standby voltage supply input for low-power standby operation * Flash EEPROM (16 and 32 Kbyte modules) -- Bulk erase mode -- Can provide a contiguous 48 Kbyte address space * 2 Kbyte Flash EEPROM with Independently Erasable Blocks (BEFLASH) -- Bulk/block erase and byte/word programming with 12 volt external input
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MC68HC916X1 MC68HC916X1TS/D
1.2 Block Diagram
VFPE32K PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PGP5 OC2/OC1/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 RxD TxD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 VSTBY IC4/OC5/OC1 OC4/OC1 OC3/OC1 OC2/OC1 OC1 IC3 IC2 IC1 TxD PCS3 PCS2 PCS1 PCS0 SCK MOSI MISO
CHIP SELECTS GPT 32K FLASH EEPROM SCIM
CS[10:0] BR BG BGACK
ADDR23/CS10/ECLK ADDR19/CS6/PC3 FC2/CS5/PC2 FC1/PC1 FC0/CS3/PC0 BR/CS0 BG/CSM BGACK/CSE PA[7:0]/ADDR[18:11] PB[7:0]/ADDR[10:3] ADDR[2:0]
PORT GP CONTROL
FC2 FC1 FC0 ADDR[23:19]
PORT QS CONTROL
QSM
2K SRAM EBI
SIZ1 SIZ0 AS DS DSACK1
CONTROL PORT A/B
ADDR[18:3]
CONTROL PORT C
V DDA VSSA
ADC
AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VRH VRL AN5 AN4 AN3 AN2 AN1 AN0 PORT AD CONTROL
2K BLOCK ERASABLE FLASH EEPROM 16K FLASH EEPROM
CONTROL PORT E
VDD VSS
IMB
SIZ1/PE7 SIZ0/PE6 AS/PE5 DS/PE4 DSACK1/PE1 R/W RESET BERR
CPU16
CONTROL PORT G/H CONTROL PORT F
DATA[15:0] IRQ[7:6]
PG[7:0]/DATA[15:8] PH[7:0]/DATA[7:0] IRQ7/PF7 IRQ6/PF6 MODCLK/PF0 CLKOUT XTAL
MODCLK CLOCK DSCLK DSO DSI IPIPE1 IPIPE0 BKPT
VFPE2K
TEST
QUOT FREEZE
CONTROL
BKPT/DSCLK IPIPE1/DSI IPIPE0/DSO
CONTROL
TSC
EXTAL XFC VDDSYN
TSC FREEZE/QUOT
916X1 BLOCK
Figure 1 MC68HC916X1 Block Diagram
MC68HC916X1 MC68HC916X1TS/D
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1.3 Pin Assignments
VRL PADA1/AN1 PADA2/AN2 PADA3/AN3 PADA4/AN4 PADA5/AN5 VFPE32K IPIPE0/DSO IPIPE1/DSI BKPT/DSCLK ADDR23/CS10/ECLK VDDE ADDR19/CS6 VSSE FC2/CS5 FC1 FC0/CS3 BGACK/CSE BG/CSM VSSI VDDI BR/CS0 PH0/DATA0 PH1/DATA1 PH2/DATA2 PH3/DATA3 VSSE PH4/DATA4 VDDE PH5/DATA5 VRH PADA0/AN0 VSSA VDDA VSSE ADDR1 VDDE ADDR2 PB0/ADDR3 PB1/ADDR4 PB2/ADDR5 PB3/ADDR6 PB4/ADDR7 PB5/ADDR8 PB6/ADDR9 VSSI PB7/ADDR10 PA0/ADDR11 PA1/ADDR12 PA2/ADDR13 VDDE PA3/ADDR14 VSSE PA4/ADDR15 PA5/ADDR16 PA6/ADDR17 PA7/ADDR18 VFPE2K PGP0/IC1 PGP1/IC2 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
PGP2/IC3 PGP3/OC1 PGP4/OC2/OC1 VDDE PGP5/OC3/OC1 VSSE PGP6/OC4/OC1 PGP7/IC4/OC5/OC1 PAI PWMA PWMB PCLK VSTBY XTAL VDDSYN EXTAL VSSI VDDI XFC VDDE VSSE CLKOUT FREEZE/QUOT PQS7/TXD RXD PQS6/PCS3 PQS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS PQS2/SCK
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MC68HC916X1
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PH6/DATA6 PH7/DATA7 PG0/DATA8 PG1/DATA9 PG2/DATA10 PG3/DATA11 PG4/DATA12 VDDE PG5/DATA13 VSSE PG6/DATA14 PG7/DATA15 ADDR0 PE1/DSACK1 PE4/DS VSSI PE5/AS PE6/SIZ0 PE7/SIZ1 R/W MODCLK PF6/IRQ6 VDDE PF7/IRQ7 VSSE TSC BERR RESET PQS0/MISO PQS1/MOSI
916X1 120-PIN QFP
Figure 2 MC68HC916X1 Pin Assignments 1.4 Address Map Figure 3 is a map of the MCU internal addresses. Although there are 24 IMB address lines, the CPU16 uses only ADDR[19:0]. ADDR[23:20] are driven to the same logic state as ADDR19. Addresses $080000 to $F7FFFF are not accessible. The 2-Kbyte SRAM, 16-Kbyte and 32-Kbyte flash EEPROM arrays are positioned by the base address registers in their respective control blocks. Reset disables the SRAM array. Unimplemented blocks are mapped externally.
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MC68HC916X1 MC68HC916X1TS/D
$FFF000 $FFF700 ADC (64 BYTES) 2K BLOCK ERASABLE FLASH EEPROM CONTROL (32 BYTES) 16K FLASH EEPROM CONTROL (32 BYTES) 32K FLASH EEPROM CONTROL 2K BLOCK ERASABLE FLASH EEPROM ARRAY
$FFF740 $FFF7A0 $FFF7C0 $FFF800 $FFF820 $FFF840 $FFF900 $FFF940 $FFFA00 $FFFA80 $FFFB00 $FFFB08
(MAPPED TO 2K BOUNDARY)
(MAPPED TO 16K BOUNDARY)
16K FLASH EEPROM ARRAY
GPT (64 BYTES) 32K FLASH EEPROM ARRAY (MAPPED TO 32K BOUNDARY)
SCIM (128 BYTES)
SRAM CTRL (8 BYTES)
(MAPPED TO 2K BOUNDARY)
2K SRAM ARRAY
$FFFC00 QSM (512 BYTES)
$FFFE00 $FFFFFF
916X1 ADDRESS MAP
Figure 3 MC68HC916X1 Address Map In the address map, Y = M111, where M reflects the state of the module mapping (MM) bit in the SCIM module configuration register (SCIMCR). On M68HC16 microcontrollers, Y must equal $F. If M equals 0, IMB modules become inaccessible until a reset occurs. The SCIMCR MM bit can be written only once after reset. 1.5 Intermodule Bus The IMB is a standardized bus developed to facilitate design of modular microcontrollers. It contains circuitry that supports exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another and with external components via the IMB. Although the full IMB supports 24 address and 16 data lines, this MCU uses only 20 address lines. Because the CPU16 uses only 20 address lines, ADDR[23:20] follow the state of ADDR19.
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2 Signal Descriptions
2.1 Pin Characteristics Table 2 shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. Refer to Table 4 for a description of output drivers. An entry in the discrete I/O column of the MCU pin characteristics table indicates that a pin has an alternate I/O function. The port designation is given when it applies. Refer to Figure 1 for information about port organization. Table 2 MCU Pin Characteristics
Pin Mnemonic ADDR23/CS10/ECLK ADDR19/CS6 ADDR[18:11] ADDR[10:3] ADDR[2:0] AN[5:0]1 AS BERR2 BG/CSM BGACK/CSE BKPT/DSCLK BR/CS0 CLKOUT DATA[15:8] DS DSACK1 EXTAL3 FC[2:0]/CS5, CS3 FREEZE/QUOT IC4/OC5 IC[3:1] IPIPE1/DSI IPIPE0/DSO IRQ[7:6] MISO MODCLK1 MOSI OC[4:1] PAI4 PCLK4 PCS0/SS PCS[3:1] PWMA, PWMB5 R/W
1
Output Driver A A A A A -- B B B B -- B A Aw Aw B B -- A A A A A A B Bo B Bo A -- -- Bo Bo A A
Input Synchronized Y Y Y Y -- Y Y Y -- Y Y Y -- Y Y Y Y -- -- -- Y Y Y -- Y Y Y Y Y Y Y Y Y Y --
Input Hysteresis N N Y Y -- Y Y N -- N N N -- Y Y Y N -- -- -- Y Y Y -- Y Y Y Y Y Y Y Y Y Y --
Discrete I/O -- O I/O I/O -- I I/O -- -- -- -- -- -- I/O I/O I/O I/O -- O -- I/O I/O -- -- I/O I/O I/O I/O I/O I I I/O I/O O --
Port Designation -- PC3 PA[7:0] PB[7:0] -- PADA[5:0] PE5 -- -- -- -- -- -- PG[7:0] PH[7:0] PE4 PE1 -- PC[2:0] -- PGP7 PGP[2:0] -- -- PF[7:6] PQS6 PF0 PQS7 PGP[6:3] -- -- PQS1 PQS[4:2] -- --
DATA[7:0]1
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MC68HC916X1 MC68HC916X1TS/D
Table 2 MCU Pin Characteristics (Continued)
Pin Mnemonic RESET RXD SCK SIZ[1:0] TSC TXD XFC3 XTAL
3
Output Driver Bo Bo Bo B -- Bo -- --
Input Synchronized Y Y Y Y Y Y -- --
Input Hysteresis Y Y Y N Y Y -- --
Discrete I/O -- I/O I/O I/O -- I/O -- --
Port Designation -- -- PQS5 PE[7:6] -- PQS0 -- --
1. DATA[15:0] are synchronized during reset only. MODCLK and ADC pins are synchronized only if used as input port pins. 2. BERR only synchronized if late BERR. 3. EXTAL, XFC, and XTAL are clock reference connections. 4. PAI and PCLK can be used for discrete input, but are not part of an I/O port. 5. PWMA and PWMB can be used for discrete output, but are not part of an I/O port.
2.2 MCU Power Connections Table 3 MCU Power Connections
Pin VDDA/VSSA VSSSYN VDDE, VSSE VDDI, VSSI VSTBY VFPE2K VFPE32K Description A/D converter power Clock synthesizer power External periphery power (source and drain) Internal module power (source and drain) Standby RAM power/clock synthesizer power 2K block erasable flash (shared with 16K flash EEPROM array) program/erase power 32K flash EEPROM array program/erase power
2.3 MCU Output Driver Types Table 4 MCU Output Driver Types
Type A Aw B I/O O O O Description Output-only signals that are always driven; no external pull-up required. Type A output with weak P-channel pull-up during reset. Three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level while the pin is in the high-impedance state. Type B output that can be operated in an open-drain mode.
Bo
O
MC68HC916X1 MC68HC916X1TS/D
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2.4 MCU Signal Characteristics Table 5 MCU Signal Characteristics
Signal Name ADDR[19:0] AN[5:0] AS BERR BG BGACK BKPT BR CLKOUT CS10, CS[6:5], CS3, CS0 CSE CSM DATA[15:0] DS DSACK1 DSCLK DSI DSO ECLK EXTAL FREEZE IC[4:1] IPIPE0 IPIPE1 IRQ[7:6] MISO MODCLK MOSI OC[5:1] PAI PCLK PCS0/SS PCS[3:1] PWMA, PWMB QUOT R/W RESET RXD SCK SIZ[1:0] TSC TXD XFC XTAL MCU Module SCIM ADC SCIM SCIM SCIM SCIM CPU16 SCIM SCIM SCIM SCIM SCIM SCIM SCIM SCIM CPU16 CPU16 CPU16 CPU16 CPU16 SCIM GPT CPU16 CPU16 SCIM QSM SCIM QSM GPT GPT GPT QSM QSM GPT SCIM SCIM SCIM QSM QSM SCIM SCIM QSM SCIM SCIM Signal Type Bus Input Output Input Output Input Input Input Output Output Output Output Bus Output Input Input Input Output Output Input Output Input Output Output Input Input/Output Input Input/Output Output Input Input Input Input Output Output Output Input/Output Input Input/Output Output Input Input/Output Input Output Active State -- -- 0 0 0 0 0 0 -- 0 0 0 -- 0 0 Serial Clock Serial Data Serial Data -- -- 1 -- -- -- 0 Serial Data -- Serial Data -- -- -- 0 0 -- -- -- 0 -- -- -- 1 -- -- --
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MC68HC916X1 MC68HC916X1TS/D
2.5 MCU Signal Function Table 6 MCU Signal Function
Signal Name Address Bus ADC Analog Input Address Strobe Bus Grant Bus Grant Acknowledge Bus Error Breakpoint Bus Request System Clockout Emulation Mode Chip-Selects Mnemonic ADDR[19:0] AN[5:0] AS BG BGACK BERR BKPT BR CLKOUT CSE, CSM Inputs to ADC multiplexer Indicates that a valid address is on the address bus Indicates that the MCU has relinquished the bus Indicates that an external device has assumed bus mastership Indicates that a bus error has occurred Signals a hardware breakpoint to the CPU Indicates that an external device requires bus mastership System clock output CSE selects external emulation devices at internally-mapped addresses. It is used to emulate I/O ports. CSM has no function on the MC68HC916X1. It is driven high if the SCIM is configured for emulation mode. Select external devices at programmed addresses 16-bit data bus During a read cycle, indicates that an external device should place valid data on the data bus. During a write cycle, indicates that valid data is on the data bus. Asserted by external devices during asynchronous transfers to indicate receipt of data and width of receiving port Function 20-bit address bus used by CPU16
Chip-Selects Data Bus Data Strobe
CS10, CS[6:5], CS3, CS0 DATA[15:0] DS
Data and Size Acknowledge Development Serial In, Out, Clock External Clock Crystal Oscillator Function Codes Freeze Instruction Pipeline Interrupt Request Master In Slave Out Clock Mode Select Master Out Slave In Peripheral Chip-Selects Port A Port B Port C Port E Port F Port G Port GP Port H Port QS Pulse Accumulator Input
DSACK1
DSI, DSO, DSCLK Serial I/O and clock for background debug mode ECLK EXTAL, XTAL FC[2:0] FREEZE IPIPE[1:0] IRQ[7:6] MISO MODCLK MOSI PCS[3:0] PA[7:0] PB[7:0] PC[3:0] PE1, PE[7:4] PF0, PF[7:6] PG[7:0] PGP[7:0] PH[7:0] PQS[7:0] PAI M6800 bus clock output Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used Identify processor state and current address space Indicates that the CPU16 has entered background mode Indicates instruction pipeline activity Request interrupt service from the CPU16 Serial input to SPI in master mode; serial output from SPI in slave mode Selects the source and type of system clock Serial output from SPI in master mode; serial input to SPI in slave mode QSPI peripheral chip selects Port A digital input or output signals Port B digital input or output signals Port C digital input/output port signals Port E digital I/O port signals Port F digital I/O port signals Port G digital I/O signals GPT digital I/O port signal Port H digital I/O signal QSM digital I/O port signal Input to the GPT pulse accumulator
MC68HC916X1 MC68HC916X1TS/D
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Table 6 MCU Signal Function (Continued)
Signal Name Quotient Out Read/Write Reset Receive Data (SCI) Serial Clock (QSPI) Size Slave Select Three-State Control Transmit Data (SCI) External Filter Capacitor Mnemonic QUOT R/W RESET RXD SCK SIZ[1:0] SS TSC TXD XFC Function Provides the quotient bit of the polynomial divider Indicates the direction of data transfer on the bus System reset Serial input to the SCI Clock output from QSPI in master mode; clock input to QSPI in slave mode Indicates the number of bytes to be transferred during a bus cycle Causes serial transmission when QSPI is in slave mode; causes mode fault in master mode Places all output drivers in a high-impedance state Serial output from the SCI Connection for external phase-locked loop filter capacitor
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MC68HC916X1 MC68HC916X1TS/D
3 Single-Chip Integration Module
The single-chip integration module (SCIM) consists of six submodules that, with a minimum of external devices, control system startup, initialization, configuration, and the external bus. Figure 4 shows the SCIM block diagram.
SYSTEM CONFIGURATION XTAL CLKOUT EXTAL MODCLK
CLOCK SYNTHESIZER
SYSTEM PROTECTION
CHIP SELECTS
CHIP SELECTS
EXTERNAL BUS INTERFACE
EXTERNAL BUS RESET TSC
FACTORY TEST
FREEZE/QUOT
S(C)IM BLOCK
Figure 4 Single-Chip Integration Module Block Diagram 3.1 Overview The system configuration block controls MCU configuration and operating mode. The system clock generates clock signals used by the SCIM, other IMB modules, and external devices. In addition, a periodic interrupt generator supports execution of time-critical control routines. The system protection block provides bus and software watchdog monitors. The chip-select block provides five general-purpose chip-select signals and two emulation-support chip-select signals. The general-purpose chip-select signals have associated base address registers and option registers. The external bus interface handles the transfer of information between IMB modules and external address space. The system test block incorporates hardware necessary for testing the MCU. It is used to perform factory tests, and its use in normal applications is not supported. Table 7 shows the SCIM address map, which occupies 128 bytes. Unused registers within the 128byte address space return zeros when read.
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Table 7 SCIM Address Map
Address $YFFA00
1
15
8
7
0
SCIM MODULE CONFIGURATION REGISTER (SCIMCR) FACTORY TEST REGISTER (SCIMTR) CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR) NOT USED PORT A DATA REGISTER (PORTA) PORT G DATA REGISTER (PORTG) PORT G DATA DIRECTION (DDRG) NOT USED NOT USED PORT A/B DATA DIRECTION (DDRAB) NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED RESET STATUS REGISTER (RSR) MODULE TEST E (SCIMTRE) PORT B DATA REGISTER (PORTB) PORT H DATA REGISTER (PORTH) PORT H DATA DIRECTION (DDRH) PORT E DATA (PORTE0) PORT E DATA (PORTE1) PORT E DATA DIRECTION (DDRE) PORT E PIN ASSIGNMENT (PEPAR) PORT F DATA (PORTF0) PORT F DATA (PORTF1) PORT F DATA DIRECTION (DDRF) PORT F PIN ASSIGNMENT (PFPAR) SYSTEM PROTECTION CONTROL (SYPCR)
$YFFA02 $YFFA04 $YFFA06 $YFFA08 $YFFA0A $YFFA0C $YFFA0E $YFFA10 $YFFA12 $YFFA14 $YFFA16 $YFFA18 $YFFA1A $YFFA1C $YFFA1E $YFFA20 $YFFA22 $YFFA24 $YFFA26 $YFFA28 $YFFA2A $YFFA2C $YFFA2E $YFFA30 $YFFA32 $YFFA34 $YFFA36 $YFFA38 $YFFA3A $YFFA3C $YFFA3E $YFFA40 $YFFA42 $YFFA44 $YFFA46 $YFFA48 $YFFA4A $YFFA4C $YFFA4E
PERIODIC INTERRUPT CONTROL (PICR) PERIODIC INTERRUPT TIMING (PITR) NOT USED NOT USED NOT USED NOT USED SOFTWARE SERVICE (SWSR) PORT F EDGE DETECT FLAGS (PORTFE) PORT F EDGE DETECT INTERRUPT VECTOR (PFIVR) PORT F EDGE DETECT INTERRUPT LEVEL (PFLVR) RESERVED TEST MODULE MASTER SHIFT A (TSTMSRA) TEST MODULE MASTER SHIFT B (TSTMSRB) TEST MODULE SHIFT COUNT A (TSTSCA) TEST MODULE SHIFT COUNT B (TSTSCB)
TEST MODULE REPETITION COUNTER (TSTRC) TEST MODULE CONTROL (CREG) TEST MODULE DISTRIBUTED REGISTER (DREG) RESERVED RESERVED NOT USED RESERVED CHIP-SELECT PIN ASSIGNMENT 0 (CSPAR0) CHIP-SELECT PIN ASSIGNMENT 1 (CSPAR1) CHIP-SELECT BASE ADDRESS BOOT (CSBARBT) CHIP-SELECT OPTION BOOT (CSORBT) CHIP-SELECT BASE 0 (CSBAR0) CHIP-SELECT OPTION 0 (CSOR0) PORT C DATA (PORTC)
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MC68HC916X1 MC68HC916X1TS/D
Table 7 SCIM Address Map (Continued)
Address $YFFA50 $YFFA52 $YFFA54 $YFFA56 $YFFA58 $YFFA5A $YFFA5C $YFFA5E $YFFA60 $YFFA62 $YFFA64 $YFFA66 $YFFA68 $YFFA6A $YFFA6C $YFFA6E $YFFA70 $YFFA72 $YFFA74 $YFFA76 $YFFA78 $YFFA7A $YFFA7C $YFFA7E 15 8 7 0 RESERVED RESERVED RESERVED RESERVED CHIP-SELECT BASE 3 (CSBAR3) CHIP-SELECT OPTION 3 (CSOR3) RESERVED RESERVED CHIP-SELECT BASE 5 (CSBAR5) CHIP-SELECT OPTION 5 (CSOR5) CHIP-SELECT BASE 6 (CSBAR6) CHIP-SELECT OPTION 6 (CSOR6) CHIP-SELECT BASE 7 (CSBAR7) CHIP-SELECT OPTION 7 (CSOR7) CHIP-SELECT BASE 8 (CSBAR8) CHIP-SELECT OPTION 8 (CSOR8) CHIP-SELECT BASE 9 (CSBAR9) CHIP-SELECT OPTION 9 (CSOR9) CHIP-SELECT BASE 10 (CSBAR10) CHIP-SELECT OPTION 10 (CSOR10) RESERVED RESERVED RESERVED RESERVED
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIMCR.
3.2 System Configuration The MCU can operate as a stand-alone device (single-chip mode), with a 20-bit external address bus and an 8-bit external data bus, or with a 20-bit external address bus and a 16-bit external data bus. SCIM pins can be configured for use as I/O ports or programmable chip select signals. Refer to 3.9 Chip Selects and 3.10 General-Purpose Input/Output for more information. System configuration is determined by setting bits in the SCIM configuration register (SCIMCR), and by asserting MCU pins during reset. SCIMCR -- SCIM Module Configuration Register
15 RESET: 0 EXOFF 14 13 FRZSW FRZBM 0 0 CPUD1 * 12 RSVD2 0 11 10 0 0 0 9 SHEN 0 8 7 SUPV 1 6 MM 1 ABD1 * 5 RWD1 * 4 3 2 IARB 1 1 1 1
$YFFA00
1 0
1. Reset state is mode-dependent. Refer to the following bit descriptions. 2. This bit is reserved for future use. Ensure that initialization software does not change its value (it should always read zero).
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 15
The module configuration register controls system configuration. It can be read or written at any time, except for the module mapping (MM) bit, which must remain set to one and can only be written once. EXOFF -- External Clock Off 0 = The CLKOUT pin is driven from an internal clock source. 1 = The CLKOUT pin is placed in a high-impedance state. FRZSW -- Freeze Software Watchdog Enable 0 = When FREEZE is asserted, the software watchdog continues to run. 1 = When FREEZE is asserted, the software watchdog is disabled. FRZBM -- Freeze Bus Monitor Enable 0 = When FREEZE is asserted, the bus monitor continues to operate. 1 = When FREEZE is asserted, the bus monitor is disabled. CPUD -- CPU Development Support Disable 0 = Instruction pipeline signals available on pins IPIPE0 and IPIPE1 1 = Pins IPIPE0 and IPIPE1 placed in high-impedance state unless a breakpoint occurs CPUD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode. SHEN[1:0] -- Show Cycle Enable This field determines how the external bus is driven during internal transfer operations. A show cycle allows internal transfers to be monitored externally. Table 8 shows whether show cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict, external peripherals must not be enabled during show cycles. Table 8 Show Cycle Enable Field
SHEN 00 01 10 11 Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled, internal activity is halted by a bus grant
SUPV -- Supervisor/Unrestricted Data Space This bit has no effect because the CPU16 always operates in the supervisor mode. MM -- Module Mapping 0 = Internal modules are addressed from $7FF000 - $7FFFFF. 1 = Internal modules are addressed from $FFF000 - $FFFFFF. The logic state of MM determines the value of ADDR23 for IMB module addresses. Because ADDR[23:20] are driven to the same state as ADDR19, MM must be set to one. If MM is cleared, IMB modules are inaccessible. This bit can be written only once after reset. ABD -- Address Bus Disable 0 = Pins ADDR[2:0] operate normally. 1 = Pins ADDR[2:0] are disabled. ABD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode. ABD can be written only once after reset.
MOTOROLA 16
MC68HC916X1 MC68HC916X1TS/D
RWD -- Read/Write Disable 0 = R/W signal operates normally 1 = R/W signal placed in high-impedance state. RWD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode. RWD can be written only once after reset. IARB[3:0] -- Interrupt Arbitration Each module that can generate interrupts, including the SCIM, has an IARB field. Each IARB field can be assigned a value from $0 to $F. During an interrupt acknowledge cycle, IARB permits arbitration among simultaneous interrupts of the same priority level. The reset value of the SCIM IARB field is $F. This prevents SCIM interrupts from being discarded. Initialization software must set the IARB field to a lower value if lower priority interrupts are to be arbitrated. 3.2.1 Operating Modes During reset, the SCIM configures itself according to the states of the DATA[11:0], BERR, MODCLK, and BKPT pins. DATA[11:0] provide pin configuration information. BERR, MODCLK, and BKPT determine basic operation. The SCIM can be configured to operate in one of three modes: 16-bit expanded, 8-bit expanded, and single chip. Operating mode is determined by the value of the DATA1 and BERR signals coming out of reset. Table 9 shows the basic configuration options. Table 9 Basic Configuration Options
Select Pin MODCLK Default Function (Pin Left High) Synthesized System Clock Background Mode Disabled Expanded Mode 8-Bit Expanded Mode Alternate Function (Pin Pulled Low) External System Clock Background Mode Enabled Single-Chip Mode 16-Bit Expanded Mode
BKPT BERR DATA1 (if BERR = 1)
BERR, BKPT, and MODCLK do not have internal pull-ups and must be driven to the desired state during reset. Operating mode determines which address and data bus lines are used and which general-purpose I/O ports are available. Table 10 is a summary of bus and port configuration options. Table 10 Bus and Port Configuration Options
Mode 16-Bit Expanded 8-Bit Expanded Single Chip Address Bus ADDR[18:3] ADDR[18:3] None Data Bus DATA[15:0] DATA[15:8] None I/O Ports -- DATA[7:0] = Port H ADDR[18:11] = Port A ADDR[10:3] = Port B DATA[15:8] = Port G DATA[7:0] = Port H
Many pins on the MC68HC916X1, including data and address bus pins, have multiple functions. Reset value for these pins depends on operating mode. In expanded mode, the values of DATA[11:0] during reset determine the function of these pins. The functions of some pins can be changed by writing to the appropriate pin assignment register. Data bus pins have internal pull-ups and must be pulled low to achieve the alternate configuration desired. The following tables contain a summary of pin configuration options for each operating mode.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 17
3.2.2 16-Bit Expanded Mode In 16-bit expanded mode, (BERR = 1, DATA1 = 0) pins ADDR[18:3] and DATA[15:0] are configured as address and data pins, respectively. The alternate functions for these pins as ports A, B, G, and H are unavailable. Table 11 is a summary of pin function options for 16-bit data bus operation. Table 11 16-Bit Expanded Mode Reset Configuration
Pin(s) Affected BR/CS0 FC0/CS3/PC0 FC1/PC1 FC2/CS5/PC2 ADDR19/CS6/PC3 ADDR23/CS10/ECLK DSACK1/PE1 DS/PE4 AS/PE5 SIZ0/PE6 SIZ1/PE7 MODCLK/PF0 IRQ[7:6]/PF[7:6] BGACK/CSE BG/CSM Reserved Emulation Mode (SCIM) STOP Mode (BEFLASH) Select Pin DATA2 Default Function (Pin Held High) CS0 CS3 FC1 CS5 CS6 CS10 DSACK1 DS AS SIZ0 SIZ1 MODCLK IRQ[7:6] BGACK BG Normal Operation Disabled Array Enabled
5
Alternate Function (Pin Held Low) BR FC0 FC1 FC2 ADDR19 ADDR23 PE1 PE4 PE5 PE6 PE7 PF0 PF[7:6] CSE2 CSM3 Reserved Enabled Array Disabled
DATA31 DATA71 DATA8
DATA9 DATA10 DATA114 DATA10 DATA15
1. CS[9:7] outputs are not available on the MC68HC916X1. Corresponding pin assignment register fields (CSPA1[3:1]) are affected by the state of DATA[6:4] during reset. 2. CSE is enabled when DATA10 and DATA1 = 0 during reset. 3. CSM is enabled when DATA13, DATA10 and DATA1 = 0 during reset. 4. DATA11 must remain high during reset to ensure normal operation of MCU. 5. Driven to put BEFLASH in STOP mode. STOP mode disabled when DATA15 is held high and STOP shadow bit is cleared.
3.2.3 8-Bit Expanded Mode In 8-bit expanded mode (BERR = 1, DATA1 = 1), pins DATA[7:0] are configured as an 8-bit I/O port. Pins DATA[15:8] are configured as data pins. Pins ADDR[18:3] are configured as address pins. Emulator mode is always disabled. Table 12 is a summary of pin function selections for 8-bit data bus operation.
MOTOROLA 18
MC68HC916X1 MC68HC916X1TS/D
Table 12 8-Bit Expanded Mode Reset Configuration
Pin(s) Affected BR/CS0 FC0/CS3/PC0 FC1/PC1 FC2/CS5/PC2 ADDR19/CS6/PC0 ADDR23/CS10/ECLK DSACK1/PE1 DS/PE4 AS/PE5 SIZ0/PE6 SIZ1/PE7 MODCLK/PF0 IRQ[7:6]/PF[7:6] BGACK/CSE BG/CSM Select Pin N/A1 Default Function (Pin Held High) CS0 CS3 FC1 CS5 CS6 CS10 DSACK1 DS AS SIZ0 SIZ1 MODCLK IRQ[7:6] BGACK BG Alternate Function (Pin Held Low) CS0 CS3 FC1 CS5 CS6 CS10 PE1 PE4 PE5 PE6 PE7 PF0 PF[7:6] BGACK BG
N/A1 DATA8
DATA9 N/A1
1. These pins have only one reset configuration in 8-bit expanded mode.
3.2.4 Single-Chip Mode In single-chip mode, when BERR = 0 during reset, ADDR[18:3] are configured as 8-bit I/O ports (port A and port B) and DATA[15:0] are configured as 8-bit I/O ports (port G and port H). There is no external data bus path. Expanded mode configuration options are not available: I/O ports A, B, E, F, G, and H are always selected. BERR can be tied low permanently to select single-chip mode. Table 13 is a summary of SCIM pin functions during single-chip operation. Table 13 Single-Chip Mode Reset Configuration
Pin(s) Affected ADDR[18:11] ADDR[10:3] BR/CS0 FC0/CS3/PC0 FC1/PC1 FC2/CS5/PC2 ADDR19/CS6/PC3 ADDR23/CS10/ECLK DSACK1/PE1 DS/PE4 AS/PE5 SIZ0/PE6 SIZ1/PE7 MODCLK/PF0 IRQ[7:6]/PF[7:6] DATA[15:8] DATA[7:0] BGACK, CSE BG/CSM Function PA[7:0] PB[7:0] CS0 PC[3:0]
-- PE[7:4], PE1
PF0 PF[7:6] PG[7:0] PH[7:0] BGACK BG
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MOTOROLA 19
3.2.5 Emulation Support The SCIM contains logic that can be used to replace on-chip ports externally. The SCIM also contains special support logic that allows external emulation of internal ROM. This emulation support feature enables the development of a single-chip application in expanded mode. Emulator mode is a special type of 16-bit expanded operation. It is entered by holding DATA10 low, BERR high, and DATA1 low during reset. In emulator mode, all port A, B, E, G, and H data and data direction registers and the port E pin assignment register are mapped externally. Port C data, port F data and data direction registers, and port F pin assignment register are accessible normally in emulator mode. An emulator chip select (CSE) is asserted whenever any of the externally-mapped registers are addressed. The signal is asserted on the falling edge of AS. The SCIM does not respond to these accesses, allowing external logic, such as a port replacement unit (PRU) to respond. Accesses to externally mapped registers require three clock cycles. External ROM emulation is enabled by holding DATA1, DATA10, and DATA13 low during reset (BERR must be held high during reset to enable the ROM module). While ROM emulation mode is enabled, memory chip select signal CSM is asserted whenever a valid access to an address assigned to the masked ROM array is made. The ROM module does not acknowledge IMB accesses while in emulation mode. This causes the SCIM to run an external bus cycle for each access. NOTE The MC68HC916X1 flash modules do not yet support the emulator mode. If ROM emulation is enabled, the CSM chip-select will be driven high at all times. 3.3 System Clock The system clock provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in clock rate during operation. The system clock signal can be generated from one of two sources. An internal phase-locked loop (PLL) can synthesize the clock from a fast reference, or the clock signal can be input directly from an external frequency source. The fast reference is typically a 4.194 MHz crystal, but may be generated by sources other than a crystal. Keep these sources in mind while reading the rest of this section. Figure 5 is a block diagram of the clock submodule.
MOTOROLA 20
MC68HC916X1 MC68HC916X1TS/D
EXTAL
XTAL
XFC
VDDSYN
CLKOUT
CRYSTAL OSCILLATOR
/ 128
PHASE COMPARATOR
LOW-PASS FILTER
VCO
fVCO
FEEDBACK DIVIDER
W Y X
SYSTEM CLOCK
16/32 PLL BLOCK 4M
SYSTEM CLOCK CONTROL
Figure 5 System Clock Block Diagram 3.3.1 Clock Sources The state of the clock mode (MODCLK) pin during reset determines the system clock source. When MODCLK is held high during reset, the clock synthesizer generates a clock signal from an external reference frequency. The clock synthesizer control register (SYNCR) determines operating frequency and mode of operation. When MODCLK is held low during reset, the clock synthesizer is disabled and an external system clock signal must be driven onto the EXTAL pin. The input clock is referred to as fref, and can be either a crystal or an external clock source. The output of the clock system is referred to as fsys. Ensure that fref and fsys are within normal operating limits. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. Typically, a 4.194 MHz crystal is used, but the frequency may vary between 1 and 6 MHz. Figure 6 shows a recommended circuit.
C1 27 pF*
R1 1.5 K R2 1 M
XTAL EXTAL
C2 27 pF* VSSI
* RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A KDS041-18 4.194 MHz CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
16 OSCILLATOR 4M
Figure 6 System Clock Oscillator Circuit
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 21
If a fast reference frequency is provided to the PLL from a source other than a crystal, or an external system clock signal is applied through the EXTAL pin, the XTAL pin must be left floating. When an external system clock signal is applied (MODCLK = 0 during reset), the PLL is disabled. The duty cycle of the input is critical, especially at operating frequencies close to maximum. The relationship between clock signal duty cycle and clock signal period is expressed as follows:
Minimum External Clock High/Low Time Minimum External Clock Period = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------50 % - Percentage Variation of External Clock Input Duty Cycle
3.3.2 Clock Synthesizer Operation VDDSYN is used to power the clock circuits when the system clock is synthesized from either a crystal or an externally supplied reference frequency. A separate power source increases MCU noise immunity and can be used to run the clock when the MCU is powered down. A quiet power supply must be used as the VDDSYN source. Adequate external bypass capacitors should be placed as close as possible to the VDDSYN pin to assure stable operating frequency. When an external system clock signal is applied and the PLL is disabled, VDDSYN should be connected to the VSS supply. Refer to the SCIM Reference Manual (SCIMRM/AD) for more information regarding system clock power supply conditioning. A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To maintain a 50% clock duty cycle, the VCO frequency (fVCO) is either two or four times the system clock frequency, depending on the state of the X bit in SYNCR. The clock signal is fed back to a divider/ counter. The divider controls the frequency of one input to a phase comparator. The other phase comparator input is a reference signal, either from the crystal oscillator or from an external source. The comparator generates a control signal proportional to the difference in phase between the two inputs. This signal is low-pass filtered and used to correct the VCO output frequency. Filter circuit implementation can vary, depending upon the external environment and required clock stability. Figure 7 shows a recommended system clock filter network. XFC pin leakage must be kept as low as possible to maintain optimum stability and PLL performance. An external filter network connected to the XFC pin is not required when an external system clock signal is applied and the PLL is disabled (VDDSYN = 0). The XFC pin must be left floating in this case.
C3 0.1F
C1 0.1F
XFC * VDDSYN
VSSI
C4 0.01F
* MAINTAIN LOW LEAKAGE ON THE XFC NODE.
16/32 XFC CONN
Figure 7 System Clock Filter Network
MOTOROLA 22
MC68HC916X1 MC68HC916X1TS/D
The synthesizer locks when the VCO frequency is equal to fref. Lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. Whenever a comparator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come out of reset until the synthesizer locks. Crystal type, characteristic frequency, and layout of external oscillator circuitry affect lock time. When the clock synthesizer is used, SYNCR determines operating frequency and certain operating parameters. The W and Y[5:0] bits are located in the PLL feedback path, enabling frequency multiplication by a factor of up to 256. When the W or Y values change, VCO frequency changes, and there is a VCO relock delay. The SYNCR X bit controls a divide-by circuit that is not in the synthesizer feedback loop. When X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock frequency is one-fourth the VCO frequency (fVCO). When X = 1, a divide-by-two circuit is enabled, and system clock frequency is one-half the VCO frequency (fVCO). There is no relock delay when clock speed is changed by the X bit. Clock frequency is determined by SYNCR bit settings as follows: f ref ( 2W + X ) f sys = --------- [ 4 ( Y + 1 ) ( 2 )] 128 The reset state of SYNCR ($3F00) results in a power-on fsys of 16.78 MHz when the fref is 4.194 MHz. For the device to perform correctly, the clock and frequency selected by the W, X, and Y bits must be within the limits specified for the MCU. Internal VCO frequency is determined by the following equations: f VCO = 4f sys if X = 0 or f VCO = 2f sys if X = 1 3.3.3 Clock Control The clock control circuits determine system clock frequency and clock operation under special circumstances, such as loss of synthesizer reference or low-power mode. Clock source is determined by the logic state of the MODCLK pin during reset. SYNCR -- Clock Synthesizer Control Register
15 RESET: 0 W 14 X 0 1 1 1 13 12 11 Y[5:0] 1 1 1 10 9 8 7 EDIV 0 6 0 0 5 0 0 RSVD1 0 4 3 SLOCK U RSVD1 0 2
$YFFA04
1 0 STSCIM STEXT 0 0
1. Ensure that initialization software does not change the value of this bit. It should always be zero.
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of SYNCR. Bits in the lower byte show the status of, or control the operation of, internal and external clocks. Because the CPU16 always operates in supervisor mode, SYNCR can be read or written at any time.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 23
W -- Frequency Control Bit This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO speed by a factor of four. VCO relock delay is required. X -- Frequency Control Bit This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles clock speed without changing VCO speed. There is no VCO relock delay. Y[5:0] -- Frequency Control The Y field controls the modulus down counter in the synthesizer feedback loop, which effectively allows frequency multiplication by a value of Y + 1. VCO relock delay is required. EDIV -- ECLK Divide Rate 0 = ECLK frequency is system clock divided by 8 1 = ECLK frequency is system clock divided by 16 ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.9 Chip Selects for more information. SLOCK -- Synthesizer Lock Flag 0 = VCO is enabled, but has not locked 1 = VCO has locked on the desired frequency (or system clock is external) The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock status until after the user writes to SYNCR. STSCIM -- Stop Mode SCIM Clock 0 = When LPSTOP is executed, the SCIM clock is driven from the crystal oscillator and the VCO is turned off to conserve power. 1 = When LPSTOP is executed, the SCIM clock is driven from the VCO. STEXT -- Stop Mode External Clock 0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power. 1 = When LPSTOP is executed, the CLKOUT signal is driven from the SCIM clock, as determined by the state of the STSCIM bit. 3.3.4 Periodic Interrupt Timer The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing for the PIT is provided by a programmable prescaler driven by the system clock. PICR -- Periodic Interrupt Control Register
15 RESET: 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 PIRQL[2:0] 0 9 8 7 6 5 4 PIV[7:0] 3 2
$YFFA22
1 0
0
0
0
0
0
0
1
1
1
1
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be read or written at any time. Bits [15:11] are unimplemented and always return zero. PIRQL[2:0] -- Periodic Interrupt Request Level Table 14 shows what interrupt request level is asserted when a periodic interrupt is generated. If a PIT interrupt and an external interrupt request of the same priority occur simultaneously, the PIT interrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.
MOTOROLA 24
MC68HC916X1 MC68HC916X1TS/D
Table 14 Periodic Interrupt Request Levels
PIRQL 000 001 010 011 100 101 110 111 Interrupt Request Level Periodic Interrupt Disabled Interrupt Request Level 1 Interrupt Request Level 2 Interrupt Request Level 3 Interrupt Request Level 4 Interrupt Request Level 5 Interrupt Request Level 6 Interrupt Request Level 7
PIV[7:0] -- Periodic Interrupt Vector The bits of this field contain the vector generated in response to an interrupt from the periodic timer. When the SCIM responds, the periodic interrupt vector is placed on the bus. PITR -- Periodic Interrupt Timer Register
15 RESET: 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 PTP MODCLK 8 7 6 5 4 PITM[7:0] 3 2
$YFFA24
1 0
0
0
0
0
0
0
0
0
PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This register can be read or written at any time. PTP -- Periodic Timer Prescaler Control 1 = Periodic timer clock prescaled by a value of 512 0 = Periodic timer clock not prescaled The reset state of PTP is the complement of the state of the MODCLK signal during reset. PITM[7:0] -- Periodic Interrupt Timing Modulus Field The PIT period can be calculated as follows: ( PITM[7:0] ) ( Prescale ) ( 4 ) PIT Period = -------------------------------------------------------------------f ref where PIT Period = Periodic interrupt timer period PITM[7:0] = Periodic interrupt timer register modulus fref = Synthesizer reference of external clock input frequency Prescale = 512 or 1 depending on the state of the PTP bit in PITR 3.4 System Protection System protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. These functions reduce the number of external components required for a complete control system. Figure 8 shows the SCIM system protection block diagram.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 25
MODULE CONFIGURATION AND TEST
RESET STATUS
HALT MONITOR
RESET REQUEST
BUS MONITOR
BERR
SPURIOUS INTERRUPT MONITOR
CLOCK PRESCALER 29
SOFTWARE WATCHDOG TIMER
RESET REQUEST
PERIODIC INTERRUPT TIMER
IRQ[7:1]
SYS PROTECT BLOCK
Figure 8 System Protection Block
SYPCR -- System Protection Control Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 SWE 1 7 SWP MODCLK 6 5 SWT[1:0] 4 HME 0 3 BME 0 2
$YFFA21
1 BMT[1:0] 0
0
0
0
0
The system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can only be written once following reset, but can be read at any time. SWE -- Software Watchdog Enable 0 = Software watchdog disabled 1 = Software watchdog enabled SWP -- Software Watchdog Prescale This bit controls the value of the software watchdog prescaler. 0 = Software watchdog clock not prescaled 1 = Software watchdog clock prescaled by 512 The reset value of SWP is the complement of the state of the MODCLK pin during reset.
MOTOROLA 26
MC68HC916X1 MC68HC916X1TS/D
SWT[1:0] -- Software Watchdog Timing This field selects the divide ratio used to establish software watchdog time-out period. Table 15 gives the ratio for each combination of SWP and SWT bits. Table 15 Software Watchdog Timeout Period Divide Ratio
SWP 0 0 0 0 1 1 1 1 SWT[1:0] 00 01 10 11 00 01 10 11 Ratio 29 211 213 215 218 220 222 224
HME -- Halt Monitor Enable 0 = Disable halt monitor function 1 = Enable halt monitor function BME -- Bus Monitor Enable 0 = Disable bus monitor function for internal to external bus cycles. 1 = Enable bus monitor function for internal to external bus cycles. BMT[1:0] -- Bus Monitor Timing This field selects a bus monitor time-out period as shown in Table 16. Table 16 Bus Monitor Timeout Period
BMT[1:0] 00 01 10 11 Time-Out 64 System Clocks 32 System Clocks 16 System Clocks 8 System Clocks
3.4.1 Bus Monitor The internal bus monitor checks for excessively long response times during normal bus cycles (DSACK1) and during IACK cycles. The monitor asserts the internal BERR signal if response time is excessive. DSACK1 response times are measured in clock cycles. The maximum allowable response time can be selected by setting BMT[1:0]. The monitor does not check DSACK1 response on the external bus unless the CPU16 initiates the bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a system contains external bus masters, an external bus monitor must be implemented, and the internal to external bus monitor option must be disabled.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 27
3.4.2 Halt Monitor The halt monitor responds to an assertion of HALT on the internal bus, caused by a double bus fault. This signal is asserted by the CPU after a double bus fault occurs. A flag in the reset status register (RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhibited by the HME bit in the SYPCR. 3.4.3 Spurious Interrupt Monitor The spurious interrupt monitor causes a bus error exception if no interrupt arbitration occurs during an interrupt acknowledge cycle. The most common cause of spurious interrupts is failure to set the module configuration register IARB[3:0] to a non-zero value for modules that can generate interrupts. 3.4.4 Software Watchdog SWSR -- Software Watchdog Service Register
15 RESET: 14 13 12 UNUSED 11 10 9 8 7 6 5 4 SWSR 3 2
$YFFA27
1 0
0
0
0
0
0
0
0
0
The software watchdog service register (SWSR) is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog times out and issues a reset. This register can be written at any time, but returns zeros when read. Each time the service sequence is written, the software watchdog timer restarts. The sequence to restart consists of the following steps: * Write $55 to SWSR * Write $AA to SWSR Both writes must occur before timeout in the order listed, but any number of instructions, up to the end of the timeout period, can be executed between the two writes. Watchdog clock rate is affected by SWP and SWT[1:0] in SYPCR. When SWT[1:0] are modified, a watchdog service sequence must be performed before the new time-out period will take effect. The reset value of SWP is the complement of the state of the MODCLK pin on the rising edge of reset. Software watchdog time-out period is given in the following equation: Divide Ratio Specified by SWP and SWT[1:0] Timeout Period = ----------------------------------------------------------------------------------------------------------------------f ref 3.5 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external devices when the MCU is operating in expanded modes. In 16-bit expanded mode, the external bus has 24 address lines and 16 data lines. In 8-bit expanded mode, the external bus has 24 address lines and 8 data lines. Because the CPU16 drives only 20 of the 24 IMB address lines, ADDR[23:20] follow the output state of ADDR19.
MOTOROLA 28
MC68HC916X1 MC68HC916X1TS/D
The EBI supports byte, word, and long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data transfer size (SIZ1 and SIZ0) and the data size acknowledge pin (DSACK1). Port width is the maximum number of bits accepted or provided during a bus transfer. External devices must follow the handshake protocol described below. Control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. The selected device controls the length of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. The EBI operates in an asynchronous mode for any port width. To add flexibility and minimize the necessity for external logic, MCU chip select logic can be synchronized with EBI transfers. Chip select logic can also provide internally-generated bus control signals for these accesses. Refer to 3.9 Chip Selects for more information. 3.6 Bus Control Signals The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while the address strobe (AS) is asserted. Table 17 shows SIZ0 and SIZ1 encoding. The read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two consecutive write cycles. Table 17 Size Signal Encoding
SIZ1 0 1 1 0 SIZ0 1 0 1 0 Transfer Size Byte Word Three Byte Long Word
3.6.1 Function Codes Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be considered address extensions that automatically select one of eight address spaces to which an address applies. These spaces are designated as either user or supervisor, and program or data spaces. Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are not used. Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid while AS is asserted. Table 18 displays CPU16 address space encodings. Table 18 CPU16 Address Space Encoding
FC2 1 1 1 1 FC1 0 0 1 1 FC0 0 1 0 1 Address Space Reserved Supervisor Data Space Supervisor Program Space CPU Space
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3.6.2 Address Bus Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred during a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. The CPU16 drives ADDR[23:20] to the same logic state as ADDR19. 3.6.3 Address Strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle. 3.6.4 Data Bus Data bus signals DATA[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers data to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle. 3.6.5 Data Strobe Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle, DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle after the assertion of AS during a write cycle. 3.6.6 Bus Cycle Termination Signals During bus cycles, external devices assert a data transfer and size acknowledge signal (DSACK1). During a read cycle, the signal tells the MCU to terminate the bus cycle and to latch data. During a write cycle, the signal indicates that an external device has successfully stored data and that the cycle can terminate. The DSACK1 signal also indicates to the MCU the size of the port for the bus cycle just completed. In the MC68HC916X1, the DSACK0 pin is not provided and an external device indicates the availability of data by asserting DSACK1 regardless of port size. The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence of DSACK1 to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK1, provided BERR meets the appropriate timing requirements. The internal bus monitor can be used to generate the BERR signal for internal and internal-to-external transfers. When BERR is asserted, the CPU16 takes a bus error exception. 3.6.7 Data Transfer Mechanism MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles. The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word operation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are designated as shown in Figure 9. OP0 is the most significant byte of a long-word operand, and OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0.
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Operand 31 Long Word Three Byte Word Byte OP0 24 23
Byte Order 16 15 OP1 OP0 OP2 OP1 OP0 8 7 OP3 OP2 OP1 OP0 0
Figure 9 Operand Byte Order 3.6.8 Operand Alignment The data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the remaining number of bytes to be transferred during the current bus cycle. The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width. ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base. Bear in mind the fact that ADDR[23:20] are driven to the same logic state as ADDR19. 3.6.9 Misaligned Operands CPU16 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. The CPU16 can perform misaligned word transfers. This capability makes it software compatible with the M68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word transfers. 3.6.10 Operand Transfer Cases Table 19 shows how operands are aligned for various types of transfers. OPn entries are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle.
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Table 19 Operand Alignment
Transfer Case Byte to 16-Bit Port (Even) Byte to 16-Bit Port (Odd) Word to 16-Bit Port (Aligned) Word to 16-Bit Port (Misaligned) 3 Byte to 16-Bit Port (Aligned)2 3 Byte to 16-Bit Port (Misaligned)2 Long Word to 16-Bit Port (Aligned) Long Word to 16-Bit Port (Misaligned)
3
SIZ1 0 0 1 1 1 1 0 1
SIZ0 1 1 0 0 1 1 0 0
ADDR0 DATA[15:8] 0 1 0 1 0 1 0 1 OP0 (OP0)1 OP0 (OP0) OP0 (OP0)1 OP0 (OP0)
1 1
DATA[7:0] (OP0)1 OP0 OP1 OP0 OP1 OP0 OP1 OP0
1. Operands in parentheses are ignored by the CPU16 during read cycles. 2. Three-byte transfer cases occur only as a result of long word to byte transfer. 3. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
It is not possible to perform transfers of word operands to an 8-bit port on the MC68HC916X1 because the DSACK0 pin is not present and therefore cannot be asserted to acknowledge the transfer. This limitation can be overcome by using SCIM chip-select logic to generate DSACK for such transfers. 3.7 Resets Reset procedures handle system initialization and recovery from catastrophic failure. The MCU performs resets with a combination of hardware and software. The SCIM determines whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM selection based on hardware mode-select inputs, then passes control to the CPU16. Reset occurs when an active low logic level on the RESET pin is clocked into the SCIM. Resets are gated by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted. Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential tasks are performed during reset exception processing. Other initialization tasks must be accomplished by the exception handler routine. 3.7.1 SCIM Reset Mode Selection The logic states of certain MCU pins during reset determine SCIM operating configuration. Refer to 3.2.1 Operating Modes for more information. 3.7.2 MCU Module Pin Function During Reset Module pins usually default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. For more information, refer to the sections of this technical summary that present information about the individual modules. Table 20 is a summary of module pin functions out of reset.
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Table 20 Module Pin Functions
Module ADC Pin Mnemonic PADA[7:0]/AN[7:0] VRH VRL CPU DSI/IPIPE1 DSO/IPIPE0 BKPT/DSCLK GPT PGP7/IC4/OC5 PGP[6:3]/OC[4:1] PGP[2:0]/IC[3:1] PAI PCLK PWMA, PWMB QSM PQS7/MOSI PQS6/MISO PQS5/SCK PQS4/PCS3 PQS3/PCS2 PQS2/PCS1 PQS1/PCS0/SS PQS0/TXD RXD Function Discrete Input Reference Voltage Reference Voltage DSI/IPIPE1 DSO/IPIPE0 BKPT/DSCLK Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input Discrete Output Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input RXD
3.7.3 Reset Timing The RESET input must be asserted for a specified minimum period in order for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) to protect write cycles from being aborted by reset. While RESET is asserted, SCIM pins are either in an inactive, high-impedance state or are driven to their inactive states. When an external device asserts RESET for the proper period, reset control logic clocks the signal into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset to the entire system. If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated. After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cycles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one, reset exception processing begins. If, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-impedance state for ten cycles, then it is tested again. The process repeats until RESET is released.
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3.7.4 Power-On Reset When the SCIM clock synthesizer is used to generate system clocks, power-on reset involves special circumstances related to the application of system and clock synthesizer power. Regardless of clock source, voltage must be applied to the clock synthesizer power input pin VDDSYN, so that the MCU can operate. The following discussion assumes that VDDSYN is applied before and during reset. This minimizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset. During power-on reset, an internal circuit in the SCIM drives the IMB internal and external reset lines. The circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SCIM pins are initialized. When VDD reaches the specified minimum value, the clock synthesizer VCO begins operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse. The SCIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15 milliseconds. During this period, module port pins may be in an indeterminate state. While input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or output-only pins must condition the lines during this time. Active drivers require high-impedance buffers or isolation resistors to prevent conflict. 3.7.5 Use of Three-State Control Pin Asserting the three-state control (TSC) input causes all MCU output drivers to go to an inactive, high-impedance condition. Although TSC is an active-high input, it does not have an internal pulldown and must be tied low when not in use. TSC must remain asserted for ten system clock cycles for drivers to change state. There are certain constraints on use of TSC during power-up reset. When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer rampup time affects how long ten clock cycles take. Worst case is approximately 20 milliseconds from TSC assertion. When an external clock signal is applied (MODCLK held low during reset), pins go to high-impedance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin. NOTE When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume. 3.8 Interrupts Interrupt recognition and servicing involve complex interaction between the central processing unit, the single-chip integration module, and a device or module requesting interrupt service. The CPU16 provides for seven levels of interrupt priority (1-7), seven automatic interrupt vectors, and 200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the interrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asynchronous exception.
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Interrupt recognition is based on the states of interrupt request signals IRQ7 and the IP mask value. Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the highest priority. NOTE On the MC68HC916X1, the only external interrupts available are IRQ6 and IRQ7. The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7) from being recognized and processed. When IP contains %000, no interrupt is masked. During exception processing, the IP field is set to the priority of the interrupt being serviced. Interrupt request signals can be asserted by external devices or by microcontroller modules. Request lines are connected internally by a wired-NOR. Simultaneous requests with different priorities can be made. Internal assertion of an interrupt request signal does not affect the logic state of the corresponding MCU pin. External interrupt requests are routed to the CPU16 through the external bus interface and SCIM interrupt control logic. The CPU treats external interrupt requests as though they had come from the SCIM. External IRQ6 is an active-low level-sensitive input. External IRQ7 is an active-low transition-sensitive input. It requires both an edge and a voltage level for validity. IRQ6 is maskable. IRQ7 is non-maskable. The IRQ7 input is transition-sensitive to prevent redundant servicing and stack overflow. A non-maskable interrupt is generated each time IRQ7 is asserted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted. Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete. The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the CPU does not recognize the occurrence of the request in any way. 3.8.1 Interrupt Acknowledge and Arbitration Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a CPU space read from address $FFFFF: [IP] : 1. The CPU space read cycle performs two functions: it places a mask value corresponding to the highest priority interrupt request on the address bus, and it acquires an exception vector number from the interrupt source. The mask value also serves two purposes: it is latched into the CCR IP field to mask lower-priority interrupts during exception processing, and it is decoded by modules that have requested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them. Modules that have requested interrupt service decode the IP value placed on the address bus at the beginning of the interrupt acknowledge cycle. If their requests are at the specified IP level, they respond to the cycle. Arbitration between simultaneous requests of the same priority is performed by serial contention between module interrupt arbitration (IARB) field bit values.
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Each module that can make an interrupt service request, including the SCIM, has an IARB field in its configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111 (highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt exception when an interrupt from that module is recognized. Because the EBI manages external interrupt requests, the SCIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SCIM is %1111. The reset IARB value for all other modules is %0000. Initialization software must assign different IARB values to implement an arbitration scheme. Each module must have a unique IARB value. When two or more IARB fields have the same nonzero value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences. Arbitration must always take place, even when a single source requests service. This point is important for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SCIM wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by a bus error, which causes a spurious interrupt exception to be taken. When arbitration is complete, the dominant module must place an interrupt vector number on the data bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt acknowledge cycle is transferred to the external bus, an external device must decode the mask value and respond with a vector number, then generate bus cycle termination signals. If the device does not respond in time, a spurious interrupt exception is taken. The periodic interrupt timer (PIT) in the SCIM can generate internal interrupt requests of specific priority at predetermined intervals. By hardware convention, PIT interrupts are serviced before external interrupt service requests of the same priority. Refer to 3.3.4 Periodic Interrupt Timer for more information. 3.8.2 Interrupt Processing The following summary outlines the interrupt processing sequence. When the sequence begins, a valid interrupt service request has been detected and is pending. A. The CPU finishes higher priority exception processing or reaches an instruction boundary. B. Processor state is stacked, then the CCR PK extension field is cleared. C. The interrupt acknowledge cycle begins: 1. 2. FC[2:0] are driven to %111 (CPU space) encoding. The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; and ADDR0 = %1. Request priority is latched into the CCR IP field from the address bus.
3.
D. Modules or external peripherals that have requested interrupt service decode the priority value on ADDR[3:1]. If request priority is the same as the priority value in the address, IARB contention takes place. When there is no contention, the spurious interrupt monitor asserts BERR, and a spurious interrupt exception is processed. E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
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1.
The dominant interrupt source supplies a vector number and DSACK1 signals appropriate to the access. The CPU16 acquires the vector number. Chip-select logic asserts AVEC internally and the CPU16 generates an autovector number corresponding to interrupt priority. The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector number.
2.
3.
F. The vector number is converted to a vector address. G. The content of the vector address is loaded into the PC, and the processor transfers control to the exception handler routine. 3.9 Chip Selects Typical microcontrollers require additional hardware to provide external chip-select signals. The MC68HC916X1 includes five general-purpose programmable chip select circuits that can provide 2- to 13-clock cycle access to external memory and peripherals. Two additional chip select signals, CSE and CSM, provide emulation support. Address block sizes of 2 Kbytes to 1 Mbyte can be selected. However, because the CPU16 drives ADDR[23:20] to the same logic state as ADDR19, 512-Kbyte blocks are the largest usable size. Refer to 3.2.5 Emulation Support for more information. Chip select assertion can be synchronized with bus control signals to provide output enable, read/ write strobes, or interrupt acknowledge signals. Logic can also generate DSACK and AVEC signals internally. A single DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and control must have the same number of wait states. Chip selects can also be synchronized with the ECLK signal available on ADDR23. When a memory access occurs, chip select logic compares address space type, address, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip select registers. If all parameters match, a chip select signal is asserted. Select signals are active low. Figure 10 shows a single chip-select circuit.
INTERNAL SIGNALS ADDRESS BUS CONTROL
BASE ADDRESS REGISTER ADDRESS COMPARATOR OPTION COMPARE OPTION REGISTER TIMING AND CONTROL
PIN
AVEC DSACK
AVEC GENERATOR
DSACK GENERATOR
PIN ASSIGNMENT REGISTER
PIN DATA REGISTER
CHIP SEL BLOCK
Figure 10 Chip-Select Circuit Block Diagram
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If a chip select function is given the same address as a microcontroller module or memory array, an access to that address goes to the module or array, and the chip select signal is not asserted. Each chip-select pin has two or more functions. Configuration out of reset is determined by operating mode. In single-chip mode, all chip select pins except CS10 and CS0 are configured for alternate functions or discrete output. In expanded modes, appropriate pins are configured for chip select operation, but chip select signals cannot be asserted until a transfer size is chosen. In fully expanded mode, data bus pins can be held low to enable alternate chip-select pin functions. Table 21 shows allocation of chip selects and discrete outputs to MCU pins. Table 21 Chip Select Pin Allocation
Chip Select Function CS0 CSM CSE CS3 -- CS5 CS6 CS10 Alternate Function BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR23 Discrete Outputs Function -- -- -- PC0 PC1 PC2 PC3 ECLK
3.9.1 Chip Select Registers Pin assignment registers (CSPAR) determine functions of chip select pins. Pin assignment registers also determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC) latches discrete output data. Blocks of addresses are assigned to each chip select function. Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register (CSBAR). However, because the logic state of ADDR20 is always the same as the state of ADDR19, the largest usable block size is 512 Kbytes. Address blocks for separate chip-select functions can overlap, however, they must have the same number of wait states if they do. Chip-select option registers (CSOR) determine timing of and conditions for assertion of chip-select signals. Eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. 3.9.2 Pin Assignment Registers The pin assignment registers contain pairs of bits that determine the functions of chip-select pins. Table 22 shows pin assignment field encoding. Pin functions are shown in Tables 23 and 24 following the register diagrams. Reset state of the pin assignment registers depends on operating mode. In the register diagrams, reset values are shown in the following order: single-chip mode, 8-bit expanded mode, and 16-bit expanded mode. The notation DATA# indicates that a bit goes to the logic level of that data bus pin on reset. Data bus lines have weak pull-ups. During reset in 16-bit expanded mode, an active external device can pull the data lines low to select alternate functions.
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CSPAR0 -- Chip Select Pin Assignment Register 0
15 RESET: 0 0 0 0 14 0 CSPA0[13:12] 13 12 CSPA0[11:10] 11 10 CSPA0[9:8] 9 8 CSPA0[7:6] 7 6 CSPA0[5:4] 5 4 CSPA0[3:2] 3 2
$YFFA44
RESERVED 1 0
SINGLE-CHIP MODE 0 0 0
8-BIT EXPANDED MODE 16-BIT EXPANDED MODE 1
0
0 0 1
0 0 0
0 1 1
0 1 DATA2
0 0 1
0 0 DATA10
1 1 1
0 0 DATA10
1 1 1
1 1 DATA2
1 0 1
0 0 0
0 0 0
DATA2
CSPAR1 -- Chip Select Pin Assignment Register 1
15 RESET: 0 0 0 0 14 0 13 0 12 0 11 0 10 0 CSPA1[9:8] 9 8 CSPA1[7:6] 7 6 CSPA1[5:4] 5 4 CSPA1[3:2] 3 2
$YFFA46
CSPA1[1:0] 1 0
SINGLE-CHIP MODE 0 0 0
8-BIT EXPANDED MODE 16-BIT EXPANDED MODE 0 0
0
0 0 0
0 0 0
0 0 0
1 1 DATA7
1 0 1
0 0 DATA6
0 0 1
0 0 DATA5
0 0 1
0 0 DATA4
0 0 1
0 1 DATA3
0 0 1
Clearing both CS10 select bits (CSPAR1[9:8]) enables the M6800 bus clock (ECLK) on ADDR23. Table 22 Pin Assignment Field Encoding
Bit Pair 00 01 10 11 Description Discrete Output Alternate Function Chip Select (8-Bit Port) Chip Select (16-Bit Port)
Table 23 CSPAR0 Pin Functions
CSPAR0 Field CSPA0[13:12] CSPA0[11:10] CSPA0[9:8] CSPA0[7:6] CSPA0[5:4] CSPA0[3:2] Chip-Select Signal CS5 -- CS3 CSE CSM CS0 Alternate Signal FC2 FC1 FC0 BGACK BG BR Discrete Output PC2 PC1 PC0 -- -- --
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Table 24 CSPAR1 Pin Functions
CSPAR1 Field CSPA1[9:8] CSPA1[7:6] CSPA1[5:4] CSPA1[3:2] CSPA1[1:0] Chip-Select Signal CS10 -- -- -- CS6 Alternate Signal ADDR23 -- -- -- ADDR19 Discrete Output ECLK -- -- -- PC3
A pin programmed as a discrete output drives an external signal to the value specified in the port C data register (PORTC), with the following exceptions: * No discrete output function is available on pins BR, BG, or BGACK. * ADDR23 provides ECLK output rather than a discrete output signal. Internal chip select logic is inhibited when discrete output or alternate function are assigned. Port size is determined when a pin is assigned as a chip select. When a pin is assigned to an 8-bit port, the chip select is asserted at all addresses within the block range. If a pin is assigned to a 16bit port, the upper/lower byte field of the option register selects the byte with which the chip select is associated. 3.9.3 Base Address Registers A base address is the starting address for the block enabled by a given chip select. Block size determines the extent of the block above the base address. Each chip select has an associated base register so that an efficient address map can be constructed for each application. If a chip select is assigned an address used by a microcontroller module, the module has priority. The chip select does not respond to an access. CSBARBT -- Chip-Select Base Address Register Boot ROM
ADDR 23 0 15 ADDR 22 0 14 ADDR 21 0 13 ADDR 20 0 12 ADDR 19 0 11 ADDR 18 0 10 ADDR 17 0 9 ADDR 16 0 8 ADDR 15 0 7 ADDR 14 0 6 ADDR 13 0 5 ADDR 12 0 4 ADDR 11 0 3 2
$YFFA48
BLKSZ[2:0] 1 0
RESET:
1
1
1
CSBAR[0:10] -- Chip-Select Base Address Registers
ADDR 23 0 15 ADDR 22 0 14 ADDR 21 0 13 ADDR 20 0 12 ADDR 19 0 11 ADDR 18 0 10 ADDR 17 0 9 ADDR 16 0 8 ADDR 15 0 7 ADDR 14 0 6 ADDR 13 0 5 ADDR 12 0 4
$YFFA4C-$YFFA74
ADDR 11 0 3 2 BLKSZ[2:0] 1 0
RESET:
0
0
0
ADDR[23:20] is at the same logic level as ADDR19 during internal CPU master operation. ADDR[23:20] must match ADDR19 for the chip select to be active. NOTE CSBOOT is not present on the MC68HC916X1, however, the CSBOOT chip-select logic is still present and should be disabled before other chip-selects are initialized.
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ADDR[23:11] -- Base Address Field This field sets the starting address of a particular address space. The address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be a multiple of block size. Base address register diagrams show how base register bits correspond to address lines. Since ADDR20 = ADDR19 in the CPU16, the maximum block size is 512 Kbytes. Because ADDR[23:20] follow the logic state of ADDR19, if all 24 address lines are used, addresses from $080000 to $F7FFFF are inaccessible. BLKSZ[2:0] -- Block Size Field This field determines the size of the block above the base address that must be enabled by the chip select. Table 25 shows bit encoding for the base address registers block size field. Table 25 Block Size Field Bit Encoding
BLKSZ[2:0] 000 001 010 011 100 101 110 111 Block Size 2K 8K 16 K 64 K 128 K 256 K 512 K 512 K Address Lines Compared ADDR[23:11] ADDR[23:13] ADDR[23:14] ADDR[23:16] ADDR[23:17] ADDR[23:18] ADDR[23:19] ADDR[23:20]1
1. During normal operation ADDR[23:20] is at the same logic level as ADDR19.
3.9.4 Option Registers The option registers contain eight fields that determine timing of and conditions for assertion of chip select signals. These make the chip selects useful for generating peripheral control signals. Certain constraints set by fields in the base address register and in the option register must be satisfied to assert a chip select signal and to provide DSACK or autovector support. CSORBT -- Chip-Select Option Register Boot ROM
MODE 0 15 14 BYTE[2:0] 13 12 R/W[1:0] 11 STRB 0 10 9 DSACK[3:0] 1 0 8 7 6 SPACE[1:0] 1 1 5 4 3 IPL[2:0] 0 2
$YFFA4A
1 AVEC 0 0
RESET:
1
1
1
1
1
1
0
0
CSOR[0:10] -- Chip-Select Option Registers
MODE 0 15 14 BYTE[1:0] 13 12 R/W[1:0] 11 STRB 0 10 9 DSACK[3:0] 0 0 8 7 6 SPACE[1:0] 0 0 5 4 3
$YFFA4E-YFFA76
IPL[2:0] 0 2 1 AVEC 0 0
RESET:
0
0
0
0
0
0
0
0
NOTE CSBOOT is not present on the MC68HC916X1, however, the CSBOOT chip-select logic is still present and should be disabled before other chip-selects are initialized.
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The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers. MODE -- Asynchronous/Synchronous Mode 0 = Asynchronous mode selected 1 = Synchronous mode selected In asynchronous mode, the chip select is asserted synchronized with AS or DS. In synchronous mode, the DSACK field is not used because a bus cycle is only performed as a synchronous operation. When a match condition occurs on a chip select programmed for synchronous operation, the chip select signals the EBI that an E-clock cycle is pending. BYTE[1:0] -- Upper/Lower Byte Option This field is used only when the chip select 16-bit port option is selected in the pin assignment register. Table 26 lists upper/lower byte options. Table 26 Byte Field Bit Encoding
BYTE[1:0] 00 01 10 11 Description Disable Lower Byte Upper Byte Both Bytes
R/W[1:0] -- Read/Write This field causes a chip select to be asserted only for a read, only for a write, or for both read and write. Table 27 shows the options. Table 27 Read/Write Bit Encodings
R/W[1:0] 00 01 10 11 Description Disable Read Only Write Only Read/Write
STRB -- Address Strobe/Data Strobe 0 = Address strobe 1 = Data strobe This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe causes chip select to be asserted synchronized with data strobe. DSACK[3:0] -- Data and Size Acknowledge This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application. Table 28 shows the DSACK[3:0] field encoding. A no-wait encoding (%0000) corresponds to a three clock-cycle bus. The fast termination encoding (%1110) corresponds to a two clock-cycle bus. Microcontroller modules typically respond at this rate, but fast termination can also be used to access fast external memory.
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Table 28 DSACK Field Encoding
DSACK[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Clock Cycles Required Per Access 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 -- Wait States Inserted Per Access 0 1 2 3 4 5 6 7 8 9 10 11 12 13 - 1 (Fast Termination) External DSACK
SPACE[1:0] -- Address Space Select This option field is used to select an address space to be used by the chip select logic. The CPU16 normally operates in supervisor space. All space types can be used. Interrupt acknowledge cycles take place in CPU space. Table 29 shows address space bit encodings. Table 29 Address Space Bit Encodings
SPACE[1:0] 00 01 10 11 Address Space CPU Space User Space1 Supervisor Space Supervisor/User Space1
1. The CPU16 executes code only in supervisor mode, therefore this space field encoding has no effect. Supervisor/User space is equivalent to supervisor space encoding.
IPL[2:0] -- Interrupt Priority Level When the SPACE[1:0] field is set for CPU space (%00), chip-select logic can be used for interrupt acknowledge. During an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the value in the IPL[2:0] field. If the values are the same, then a chip-select can be asserted, provided other option register conditions are met. When the SPACE[1:0] field has any value except %00, the IPL[2:0] field determines whether an access takes place in program or data space. Table 30 shows IPL[2:0] field encoding.
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Table 30 Interrupt Priority Level Field Encoding
IPL[2:0] 000 001 010 011 100 101 110 111 SPACE[1:0] = 00 All1 IPL1 IPL2 IPL3 IPL4 IPL5 IPL6 IPL7 SPACE[1:0] = 01, 10, 11 Data or Program Data Program Reserved Reserved Data Program Reserved
1. "All" means that a chip select signal is asserted regardless of the priority of the interrupt.
This field only affects the response of chip selects and does not affect interrupt recognition by the CPU. AVEC -- Autovector Enable 0 = External interrupt vector enabled 1 = Autovector enabled This field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge cycle. It is not usually used with a chip select pin. If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = %00) and the AVEC field is set to one, the chip select automatically generates an AVEC in response to the interrupt acknowledge cycle. Otherwise, the vector must be supplied by the requesting device. 3.9.5 Port C Data Register Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is assigned as a discrete output, the value in this register appears at the output. This is a read/write register. Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read. PORTC -- Port C Data Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 7 0 0 6 RESERVED 1 5 4 PC3 1 3 PC2 1 2
$YFFA41
PC1 1 1 PC0 1 0
1
1
3.9.6 Chip Select Reset Operation The reset values of the chip select pin assignment fields in CSPAR0 and CSPAR1 depend on the operating mode selected. Refer to 3.2.1 Operating Modes and to the discussion of these registers for more information. The BYTE[1:0] field in option register CSORBT has a reset value of both bytes, but CSOR[10:0] have a reset value of disable, as they should not select external devices until an initial program sets up the base and option registers.
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3.10 General-Purpose Input/Output The SCIM contains six general-purpose input/output ports: ports A, B, E, F, G, and H. (Port C, an output-only port, is included under the discussion of chip selects). Ports A, B, and G are available in single-chip mode only and port H is available in single-chip or 8-bit expanded modes only. Ports E, F, G, and H have an associated data direction register to configure each pin as input or output. Ports A and B share a data direction register that configures each port as input or output. Ports E and F have associated pin assignment registers that configure each pin as digital I/O or an alternate function. Port F has an edge-detect flag register that indicates whether a transition has occurred on any of its pins. Table 31 shows the shared functions of the general-purpose I/O ports and the modes in which they are available. Table 31 General-Purpose I/O Ports
Port A B E F G H Shared Function ADDR[18:11] ADDR[10:3] Bus Control IRQ[7:6]/MODCLK DATA[15:8] DATA[7:0] Modes Single Chip Single Chip All All Single Chip Single Chip, 8-Bit Expanded
Access to the port A, B, E, F, G, and H data and data direction registers, and the port C, E, and F pin assignment registers require three clock cycles to ensure timing compatibility with external port replacement logic. Port registers are byte-addressable and are grouped to allow coherent word access to port data register pairs A-B and G-H, as well as word-aligned long word coherency of A-BG-H port data registers. If emulation mode is enabled, the emulation mode chip-select signal CSE is asserted whenever an access to ports A, B, E, G, and H data and data direction registers or the port E pin assignment register is made. The SCIM does not respond to these accesses, but allows external logic, such as a Motorola port replacement unit (PRU) MC68HC33 to respond. Port C data and data direction register, port F data and data direction register, and the port F pin assignment register remain accessible. A write to the port A, B, E, F, G, or H data register is stored in the internal data latch. If any port pin is configured as an output, the value stored for that bit is driven on the pin. A read of the port data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register.
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3.10.1 Ports A and B Ports A and B are available in single-chip mode only. One data direction register controls data direction for both ports. Port A and B registers can be read or written at any time the MCU is not in emulator mode. PORTA -- Port A Data Register PORTB -- Port B Data Register
PA7 U 15 PA6 U 14 PA5 U 13 PA4 U 12 PA3 U 11 PA2 U 10 PA1 U 9 PA0 U 8 PB7 U 7 PB6 U 6 PB5 U 5 PB4 U 4 PB3 U 3 PB2 U 2
$YFFA0A $YFFA0B
PB1 U 1 PB0 U 0
RESET:
DDRAB -- Port A/B Data Direction Register
15 RESET: U 0 14 0 13 0 12 0 11 0 10 0 DDA U 9 DDB U 8 7 6 5 4 DDRE 3 2
$YFFA14
1 0
U
U
U
U
U
U
U
U
U
U
U
U
U
DDA and DDB control the direction of the pin drivers for ports A and B, respectively, when the pins are configured for I/O. Setting DDA or DDB to one configures all pins in the corresponding port as outputs. Clearing DDA or DDB to zero configures all pins in the corresponding port as inputs. 3.10.2 Port E Port E can be made available in all operating modes. The state of BERR and DATA8 during reset controls whether the port E pins are used as bus control signals or discrete I/O lines. If the MCU is in emulator mode, an access of the port E data, data direction, or pin assignment registers (PORTE, DDRE, PEPAR) is forced to go external. This allows port replacement logic to be supplied externally, giving an emulator access to the bus control signals. PORTE0, PORTE1 -- Port E Data Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 PE7 U 7 PE6 U 6 PE5 U 5 PE4 U 4 3
$YFFA11, YFFA13
RESERVED U U 2 PE1 U 1 RSVD1 U 0
1. Reserved
PORTE is a single register that can be accessed in two locations. It can be read or written at any time the MCU is not in emulator mode. DDRE -- Port E Data Direction Register
15 RESET: 14 13 12 11 10 9 8 DDE7 0 7 DDE6 0 6 DDE5 0 5 DDE4 0 4 RESERVED 0 0 3 2
$YFFA15
DDE1 0 1 RSVD1 0 0
1. Reserved
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The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any bit in this register set to one configures the corresponding pin as an output. Any bit in this register cleared to zero configures the corresponding pin as an input. This register can be read or written at any time the MCU is not in emulator mode. PEPAR -- Port E Pin Assignment
15 RESET: 14 13 12 11 10 9 8 PEPA7 7 PEPA6 6 PEPA5 5 PEPA4 4 RESERVED 3 2
$YFFA17
PEPA1 1 RSVD1 0
8- AND 16-BIT EXPANDED MODES SINGLE-CHIP MODE
DATA8 0
DATA8 0
DATA8 0
DATA8 0
DATA8 0
DATA8 0
DATA8 0
DATA8 0
1. Reserved
The bits in PEPAR control the function of each port E pin. Any bit set to one defines the corresponding pin to be a bus control signal, with the function shown in Table 32. Any bit cleared to zero defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE. Table 32 Port E Pin Assignments
PEPAR Bit PEPA7 PEPA6 PEPA5 PEPA4 PEPA1 Port E Signal PE7 PE6 PE5 PE4 PE1 Bus Control Signal SIZ1 SIZ0 AS DS DSACK1
BERR and DATA8 control the state of this register following reset. If BERR and/or DATA8 are low during reset, this register is set to $00, defining all port E pins as I/O pins. If BERR and DATA8 are both high during reset, the register is set to $FF, which defines all port E pins as bus control signals. 3.10.3 Port F Port F pins can be configured as interrupt request inputs, edge-detect input/outputs, or discrete input/outputs. When port F pins are configured for edge detection, and a priority level is specified by writing a value to the port F edge-detect interrupt level register (PFLVR), port F control logic generates an interrupt request when the specified edge is detected. Interrupt vector assignment is made by writing a value to the port F edge-detect interrupt vector register (PFIVR). The edge-detect interrupt has the lowest arbitration priority in the SCIM. PORTF0, PORTF1 -- Port F Data Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 PF7 U 7 PF6 U 6 5 4 3
$YFFA19, YFFA1B
RESERVED U 2 1 PF0 U 0
U
U
U
U
A write to the port F data register is stored in the internal data latch, and if any port F pin is configured as an output, the value stored for that bit is driven on the pin. A read of PORTF returns the value on a pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the data register.
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Port F is a single register that can be accessed in two locations. It can be read or written at any time, including when the MCU is in emulator mode. DDRF -- Port F Data Direction Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 DDF7 0 7 6 5 RESERVED 0 0 4 3 2
$YFFA1D
1 DDF0 0 0
0
0
0
0
The bits in this register control the direction of port F pin drivers when the pins are configured for I/ O. Setting any bit in this register configures the corresponding pin as an output. Clearing any bit in this register configures the corresponding pin as an input. PFPAR -- Port F Pin Assignment Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 7 PFPA[7:6] 6 5 RESERVED 4 3 2
$YFFA1F
1 PFPA[1:0] 0
8- AND 16-BIT EXPANDED MODES SINGLE-CHIP MODE
DATA9 0
DATA9 0
DATA9 0
DATA9 0
DATA9 0
DATA9 0
DATA9 0
DATA9 0
The fields in this register determine the functions of pairs of port F pins. Table 33 shows port F pin assignments. Table 34 shows PFPAR pin functions. In single-chip mode (BERR = 0 during reset), this register is set to $00, defining all port F pins to be I/O pins. In 8- and 16-bit expanded modes, the state of DATA9 during reset determines the default value for PFPAR. Table 33 Port F Pin Assignments
PFPAR Field PFPA[7:6]
1
Port F Signal PF[7:6] PF[1:0]
Alternate Signal IRQ[7:6] MODCLK2
PFPA[1:0]1
1. PF[5:2] are not connected. These bits have no meaning. 2. MODCLK signal is only recognized during reset.
Table 34 PFPAR Pin Functions
PFPAx Bits 00 01 10 11 Port F Signal I/O pin without edge detect Rising edge detect Falling edge detect Interrupt request
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PORTFE -- Port F Edge-Detect Flag Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 PEF7 0 7 PEF6 0 6 5 4 RESERVED 0 3 2
$YFFA2B
1 PEF0 0 0
0
0
0
0
When the corresponding pin is configured for edge detection, a PORTFE bit is set if an edge is detected. PORTFE bits remain set, regardless of the subsequent state of the corresponding pin, until cleared. To clear a bit, first read PORTFE, then write the bit to zero. When a pin is configured for general-purpose I/O or for use as an interrupt request input, PORTFE bits do not change state. PFIVR -- Port F Edge-Detect Interrupt Vector Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 7 6 5 4 PFIVR[7:0] 3 2
$YFFA2B
1 0
0
0
0
0
0
0
0
0
This register determines which vector in the exception vector table is used for interrupts generated by the port F edge-detect logic. Program PFIVR[7:0] to the value pointing to the appropriate interrupt vector. Refer to 4 Central Processing Unit for interrupt vector assignments. PFLVR -- Port F Edge-Detect Interrupt Level Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2
$YFFA2D
PFLV[2:0] 0 1 0
0
0
PFLVR determines the priority level of the port F edge-detect interrupt. The reset value is $00, indicating that the interrupt is disabled. When several sources of interrupts from the SCIM are arbitrating for the same level, the port F edge-detect interrupt has the lowest arbitration priority. 3.10.4 Port G Port G is available in single-chip mode only. These pins are always configured for use as generalpurpose I/O in single-chip mode. 3.10.5 Port H Port H is available in single-chip and 8-bit expanded modes only. The function of these pins is determined by the operating mode. There is no pin assignment register associated with this port. PORTG -- Port G Data Register PORTH -- Port H Data Register
PG7 U 15 PG6 U 14 PG5 U 13 PG4 U 12 PG3 U 11 PG2 U 10 PG1 U 9 PG0 U 8 PH7 U 7 PH6 U 6 PH5 U 5 PH4 U 4 PH3 U 3 PH2 U 2
$YFFA0C $YFFA0D
PH1 U 1 PH0 U 0
RESET:
These port data registers can be read or written any time the MCU is not in emulation mode. Reset has no effect.
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DDRG -- Port G Data Direction Register DDRH -- Port H Data Direction Register
DDG7 0 15 DDG6 0 14 DDG5 0 13 DDG4 0 12 DDG3 0 11 DDG2 0 10 DDG1 0 9 DDG0 0 8 DDH7 0 7 DDH6 0 6 DDH5 0 5 DDH4 0 4 DDH3 0 3 DDH2 0 2
$YFFA0E $YFFA0F
DDH1 0 1 DDH0 0 0
RESET:
The bits in this register control the direction of the port pin drivers when pins are configured as I/O. Setting a bit configures the corresponding pin as an output. Clearing a bit configures the corresponding pin as an input. 3.11 Factory Test Test functions are integrated into the SCIM to support scan-based testing of the various MCU modules during production. Test submodule registers are intended for Motorola use. Register names and addresses are provided to show the user that these addresses are occupied. SCIMTR -- Single-Chip Integration Module Test Register SCIMTRE -- Single-Chip Integration Module Test Register (E Clock) TSTMSRA -- Master Shift Register A TSTMSRB -- Master Shift Register B TSTSC -- Test Module Shift Count TSTRC -- Test Module Repetition Count CREG -- Test Submodule Control Register DREG -- Distributed Register $YFFA02 $YFFA08 $YFFA30 $YFFA32 $YFFA34 $YFFA36 $YFFA38 $YFFA3A
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4 Central Processing Unit
The CPU16 is a true 16-bit, high-speed device. It was designed to give M68HC11 users a path to higher performance while maintaining maximum compatibility with existing systems. 4.1 Overview Ease of programming is an important consideration when using a microcontroller. The CPU16 instruction set is optimized for high performance. There are two 16-bit general-purpose accumulators and three 16-bit index registers. The CPU16 supports 8-bit (byte), 16-bit (word), and 32-bit (longword) load and store operations, as well as 16- and 32-bit signed fractional operations. Code development is simplified by the background debugging mode. CPU16 memory space includes a one Mbyte data space and a one Mbyte program space. Twentybit addressing and transparent bank switching are used to implement extended memory. In addition, most instructions automatically handle bank boundaries. The CPU16 includes instructions and hardware to implement control-oriented digital signal processing functions with a minimum of interfacing. A multiply and accumulate unit provides the capability to multiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accumulator. Modulo addressing supports finite impulse response filters. Use of high-level languages is increasing as controller applications become more complex and control programs become larger. These languages make rapid development of portable software possible. The CPU16 instruction set supports high-level languages. 4.2 M68HC11 Compatibility CPU16 architecture is a superset of M68HC11 CPU architecture. All M68HC11 CPU resources are available in the CPU16. M68HC11 CPU instructions are either directly implemented in the CPU16, or have been replaced by instructions with an equivalent form. The instruction sets are source code compatible, but some instructions are executed differently in the CPU16. These instructions are mainly related to interrupt and exception processing -- M68HC11 CPU code that processes interrupts, handles stack frames, or manipulates the condition code register must be rewritten. CPU16 execution times and number of cycles for all instructions are different from those of the M68HC11 CPU. As a result, cycle-related delays and timed control routines may be affected. The CPU16 also has several new or enhanced addressing modes. M68HC11 CPU direct mode addressing has been replaced by a special form of indexed addressing that uses the new IZ register and a reset vector to provide greater flexibility.
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4.3 Programming Model
20 16 15 A D E XK YK ZK SK PK CCR IX IY IZ SP PC PK 87 B 0 BIT POSITION ACCUMULATORS A AND B ACCUMULATOR D (A : B) ACCUMULATOR E INDEX REGISTER X INDEX REGISTER Y INDEX REGISTER Z STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER PC EXTENSION REGISTER ADDRESS EXTENSION REGISTER STACK EXTENSION REGISTER MAC MULTIPLIER REGISTER MAC MULTIPLICAND REGISTER 16 AM (MSB) AM (LSB) XMSK YMSK MAC ACCUMULATORMSB [35:16] MAC ACCUMULATOR LSB [15:0] MAC XY MASK REGISTER
EK
XK
YK
ZK SK
HR IR 35
Accumulator A -- 8-bit general-purpose register Accumulator B -- 8-bit general-purpose register Accumulator D -- 16-bit general-purpose register formed by concatenating accumulators A and B Accumulator E -- 16-bit general-purpose register Index Register X -- 16-bit indexing register, addressing extended by XK field in K register Index Register Y -- 16-bit indexing register, addressing extended by YK field in K register Index Register Z -- 16-bit indexing register, addressing extended by ZK field in K register Stack Pointer -- 16-bit dedicated register, addressing extended by the SK register Program Counter -- 16-bit dedicated register, addressing extended by PK field in CCR Condition Code Register -- 16-bit register containing condition flags, interrupt priority mask, and the program counter address extension field K Register -- 16-bit register made up of four 4-bit address extension fields SK Register -- 4-bit register containing the stack pointer address extension field H Register -- 16-bit multiply and accumulate input (multiplier) register I Register -- 16-bit multiply and accumulate input (multiplicand) register MAC Accumulator -- 36-bit multiply and accumulate result register XMSK, YMSK -- Determine which bits change when an offset is added
Figure 11 CPU16 Programming Model
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4.3.1 Condition Code Register
15 S MV 14 13 H EV 12 11 N 10 Z V 9 C 8 7 IP[2:0] 6 5 SM 4 3 2 PK[3:0] 1 0
S -- STOP Enable 0 = Stop clock when LPSTOP instruction is executed 1 = Perform NOP when LPSTOP instruction is executed MV -- Accumulator M overflow flag MV is set when an overflow into AM35 has occurred. H -- Half Carry Flag H is set when a carry from A3 or B3 occurs during BCD addition. EV -- Extension Bit Overflow Flag EV is set when an overflow into AM31 has occurred. N -- Negative Flag N is set when the MSB of a result register is set. Z -- Zero Flag Z is set when all bits of a result register are zero. V -- Overflow Flag V is set when a two's complement overflow occurs as the result of an operation. C -- Carry Flag C is set when a carry or borrow occurs during an arithmetic operation. This flag is also used during shift and rotate to facilitate multiple word operations. IP[2:0] -- Interrupt Priority Field The priority value in this field (0 to 7) is used to mask interrupts. SM -- Saturate Mode Bit When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is given maximum positive or negative value, depending on the state of the AM sign bit before overflow. PK[3:0] -- Program Counter Address Extension Field This field is concatenated with the program counter to form a 20-bit address. 4.4 Data Types The CPU16 supports the following data types: * Bit data * 8-bit (byte) and 16-bit (word) integers * 32-bit long integers * 16-bit and 32-bit signed fractions (MAC operations only) * 20-bit effective address consisting of 16-bit page address plus 4-bit extension A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes, and is addressed at the lower byte. Instruction fetches are always accessed on word boundaries. Word operands are normally accessed on word boundaries as well, but can be accessed on odd byte boundaries, with a substantial performance penalty. To be compatible with the M68HC11, misaligned word transfers and misaligned stack accesses are allowed. Transferring a misaligned word requires two successive byte operations.
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4.5 Addressing Modes The CPU16 provides ten types of addressing. Each type encompasses one or more addressing modes. Six CPU16 addressing types are identical to M68HC11 addressing types. All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an extension field to form a 20-bit effective address. Extension fields are part of a bank switching scheme that provides the CPU16 with a 1 Mbyte address space. Bank switching is transparent to most instructions. ADDR[19:16] of the effective address change when an access crosses a bank boundary. However, it is important to note that the value of the associated extension field is dependent on the type of instruction, and usually does not change as a result of effective address calculation. In the immediate modes, the instruction argument is contained in bytes or words immediately following the instruction. The effective address is the address of the byte following the instruction. The AIS, AIX/Y/Z, ADDD and ADDE instructions have an extended 8-bit mode where the immediate value is an 8-bit signed number that is sign-extended to 16 bits, and then added to the appropriate register. Use of the extended 8-bit mode decreases execution time. Extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective address is formed by concatenating EK and the 16-bit extension. In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used to calculate the effective address. Signed 16-bit mode and signed 20-bit mode are extensions to the M68HC11 indexed addressing mode. For 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in the index register and its associated extension field. For 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained in the index register and its associated extension field. For 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. This mode is used for JMP and JSR instructions. Inherent mode instructions use information available to the processor to determine the effective address. Operands (if any) are system resources and are thus not fetched from memory. Accumulator offset mode adds the contents of 16-bit accumulator E to one of the index registers and its associated extension field to form the effective address. This mode allows use of index registers and an accumulator within loops without corrupting accumulator D. Relative modes are used for branch and long branch instructions. A byte or word signed two's complement offset is added to the program counter if the branch condition is satisfied. The new PC value, concatenated with the PK field, is the effective address. Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is added to index register X after the effective address formed by XK and IX is used. In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped into page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vectors. To compensate for the loss of direct mode, the ZK field and index register Z have been assigned reset initialization vectors. By resetting the ZK field to a chosen page, and using 8-bit unsigned index mode with IZ, a programmer can access useful data structures anywhere in the address map.
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MC68HC916X1 MC68HC916X1TS/D
4.6 Instruction Set The CPU16 instruction set is based on that of the M68HC11, but the opcode map has been rearranged to maximize performance with a 16-bit data bus. All M68HC11 instructions are supported by the CPU16, although they may be executed differently. Most M68HC11 code runs on the CPU16 following reassembly. However, take into account changed instruction times, the interrupt mask, and the new interrupt stack frame. The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned multiplication and division. New instructions have been added to support extended addressing and digital signal processing. Table 35 is a quick reference to the entire CPU16 instruction set. Because it is only affected by a few instructions, the LSB of the condition code register is not shown in the table. Instructions that affect the interrupt mask and PK field are noted. Table 36 provides a key to the table nomenclature.
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MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary
Mnemonic Operation Description (A ) + (B) A (XK : IX) + (000 : B) XK : IX (YK : IY) + (000 : B) YK : IY (ZK : IZ) + (000 : B) ZK : IZ (AM[31:16]) + (E) AM (AM) + (E : D) AM (A) + (M) + C A Address Mode ABA ABX ABY ABZ ACE ACED ADCA Add B to A Add B to IX Add B to IY Add B to IZ Add E to AM Add E : D to AM Add with Carry to A INH INH INH INH INH INH IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z Opcode 370B 374F 375F 376F 3722 3723 43 53 63 73 1743 1753 1763 1773 2743 2753 2763 C3 D3 E3 F3 17C3 17D3 17E3 17F3 27C3 27D3 27E3 83 93 A3 37B3 37C3 37D3 37E3 37F3 2783 2793 27A3 3733 3743 3753 3763 3773 41 51 61 71 1741 1751 1761 1771 2741 2751 2761 Instruction Operand -- -- -- -- -- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll ff ff ff ii gggg gggg gggg hh ll -- -- -- Cycles 2 2 2 2 2 4 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 Condition Codes S MV H EV N ---- -- Z V C
---------------- ---------------- ---------------- -- -- -- -- -- -------- --------
----
ADCB
Add with Carry to B
(B) + (M) + C B
----
--

ADCD
Add with Carry to D
(D) + (M : M + 1) + C D
--------

ADCE
Add with Carry to E
(E) + (M : M + 1) + C E
--------

ADDA
Add to A
(A) + (M) A
----
--

MOTOROLA 56
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (B) + (M) B Address Mode ADDB Add to B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM8 IMM16 IND16, X IND16, Y IND16, Z EXT INH INH INH INH INH INH INH IMM8 IMM16 IMM8 IMM16 IMM8 IMM16 IMM8 IMM16 IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z Opcode C1 D1 E1 F1 17C1 17D1 17E1 17F1 27C1 27D1 27E1 81 91 A1 FC 37B1 37C1 37D1 37E1 37F1 2781 2791 27A1 7C 3731 3741 3751 3761 3771 2778 37CD 37DD 37ED 374D 375D 376D 3F 373F 3C 373C 3D 373D 3E 373E 46 56 66 76 1746 1756 1766 1776 2746 2756 2766 Instruction Operand ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff ii jj kk gggg gggg gggg hh ll -- -- -- ii jj kk gggg gggg gggg hh ll -- -- -- -- -- -- -- ii jj kk ii jj kk ii jj kk ii jj kk ff ff ff ii gggg gggg gggg hh ll -- -- -- Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 4 6 6 6 6 6 6 6 2 4 6 6 6 6 2 2 2 2 2 2 2 2 4 2 4 2 4 2 4 6 6 6 2 6 6 6 6 6 6 6 Condition Codes S MV H EV N ---- -- Z V C
ADDD
Add to D
(D) + (M : M + 1) D
--------

ADDE
Add to E
(E) + (M : M + 1) E
--------

ADE ADX ADY ADZ AEX AEY AEZ AIS AIX AIY AIZ ANDA
Add D to E Add D to IX Add D to IY Add D to IZ Add E to IX Add E to IY Add E to IZ Add Immediate Data to Stack Pointer Add Immediate Value to IX Add Immediate Value to IY Add Immediate Value to IZ AND A
(E) + (D) E ( XK : IX ) + ( 20 D ) XK : IX ( YK : IY ) + ( 20 D ) YK : IY ( ZK : IZ ) + ( 20 D ) ZK : IZ ( XK : IX ) + ( 20 D ) XK : IX ( YK : IY ) + ( 20 D ) YK : IY ( ZK : IZ ) + ( 20 D ) ZK : IZ (SK : SP) + (20 IMM) SK : SP (XK : IX) + (20 IMM) XK : IX (YK : IY) + (20 IMM) YK : IY (ZK : IZ) + (20 IMM) ZK : IZ (A) * (M) A
--------

---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------- ---------- ---------- -------- ---- ---- ---- 0 --
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 57
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (B) * (M) B Address Mode ANDB AND B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IMM16 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH Opcode C6 D6 E6 F6 17C6 17D6 17E6 17F6 27C6 27D6 27E6 86 96 A6 37B6 37C6 37D6 37E6 37F6 2786 2796 27A6 3736 3746 3756 3766 3776 373A 04 14 24 1704 1714 1724 1734 3704 Instruction Operand ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll jj kk ff ff ff gggg gggg gggg hh ll -- Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 4 8 8 8 8 8 8 8 2 Condition Codes S MV H EV N -------- Z V 0 C --
ANDD
AND D
(D) * (M : M + 1) D
--------
0
--
ANDE
AND E
(E) * (M : M + 1) E
--------
0
--
ANDP1 ASL
AND CCR Arithmetic Shift Left
(CCR) * IMM16 CCR

--------
ASLA
Arithmetic Shift Left A
--------

ASLB
Arithmetic Shift Left B
INH
3714
--
2
--------

ASLD
Arithmetic Shift Left D
INH
27F4
--
2
--------

ASLE
Arithmetic Shift Left E
INH
2774
--
2
--------

ASLM
Arithmetic Shift Left AM
INH
27B6
--
4
--
--
----
ASLW
Arithmetic Shift Left Word
IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT
2704 2714 2724 2734 0D 1D 2D 170D 171D 172D 173D
gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll
8 8 8 8 8 8 8 8 8 8 8
--------

ASR
Arithmetic Shift Right
--------

MOTOROLA 58
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description Address Mode ASRA Arithmetic Shift Right A INH Opcode 370D Instruction Operand -- Cycles 2 Condition Codes S MV H EV N -------- Z V C
ASRB
Arithmetic Shift Right B
INH
371D
--
2
--------

ASRD
Arithmetic Shift Right D
INH
27FD
--
2
--------

ASRE
Arithmetic Shift Right E
INH
277D
--
2
--------

ASRM
Arithmetic Shift Right AM Arithmetic Shift Right Word
INH
27BA
--
4
------
----
ASRW
IND16, X IND16, Y IND16, Z EXT If C = 0, branch (M) * (Mask) M REL8 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND16, X IND16, Y IND16, Z EXT
270D 271D 272D 273D B4 1708 1718 1728 08 18 28 38 2708 2718 2728 2738 B5 B7 BC 37A6
gggg gggg gggg hh ll rr mm ff mm ff mm ff mm gggg mm gggg mm gggg mm hh ll gggg mmmm gggg mmmm gggg mmmm hh ll mmmm rr rr rr --
8 8 8 8 6, 2 8 8 8 8 8 8 8 10 10 10 10 6, 2 6, 2 6, 2 --
--------

BCC2 BCLR
Branch if Carry Clear Clear Bit(s)
---------------- -------- 0 --
BCLRW
Clear Bit(s) in a Word
(M : M + 1) * (Mask) M:M+1
--------
0
--
BCS2 BEQ2 BGE2 BGND
Branch if Carry Set Branch if Equal Branch if Greater Than or Equal to Zero Enter Background Debug Mode Branch if Greater Than Zero Branch if Higher Bit Test A
If C = 1, branch If Z = 1, branch If N V = 0, branch If BDM enabled, begin debug; else, illegal instruction trap If Z ' (N V) = 0, branch If C ' Z = 0, branch (A) * (M)
REL8 REL8 REL8 INH
---------------- ---------------- ---------------- ----------------
BGT2 BHI2 BITA
REL8 REL8 IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z
BE B2 49 59 69 79 1749 1759 1769 1779 2749 2759 2769
rr rr ff ff ff ii gggg gggg gggg hh ll -- -- --
6, 2 6, 2 6 6 6 2 6 6 6 6 6 6 6
---------------- ---------------- -------- 0 --
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 59
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (B) * (M) Address Mode BITB Bit Test B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z REL8 REL8 REL8 REL8 REL8 REL8 REL8 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT BRN BRSET
2
Instruction Opcode C9 D9 E9 F9 17C9 17D9 17E9 17F9 27C9 27D9 27E9 BF B3 BD BB B6 BA B0 CB DB EB 0A 1A 2A 3A B1 8B 9B AB 0B 1B 2B 3B 1709 1719 1729 09 19 29 39 2709 2719 2729 2739 Operand ff ff ff ii gggg gggg gggg hh ll -- -- -- rr rr rr rr rr rr rr mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr rr mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr mm ff mm ff mm ff mm gggg mm gggg mm gggg mm hh ll gggg mmmm gggg mmmm gggg mmmm hh ll mmmm Cycles 6 6 6 2 6 6 6 6 6 6 6 6, 2 6, 2 6, 2 6, 2 6, 2 6, 2 6 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 2 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 8 8 8 8 8 8 8 10 10 10 10
Condition Codes S MV H EV N -------- Z V 0 C --
BLE2 BLS2 BLT2 BMI2 BNE2 BPL
2
Branch if Less Than or Equal to Zero Branch if Lower or Same Branch if Less Than Zero Branch if Minus Branch if Not Equal Branch if Plus Branch Always Branch if Bit(s) Clear
If Z ' (N V) = 1, branch If C ' Z = 1, branch If N V = 1, branch If N = 1, branch If Z = 0, branch If N = 0, branch If 1 = 1, branch If (M) * (Mask) = 0, branch
---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ----------------
BRA BRCLR2
Branch Never Branch if Bit(s) Set
If 1 = 0, branch If (M) * (Mask) = 0, branch
REL8 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT
---------------- ----------------
BSET
Set Bit(s)
(M) ' (Mask) M
IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND16, X IND16, Y IND16, Z EXT
--------
0
BSETW
Set Bit(s) in Word
(M : M + 1) ' (Mask) M:M+1
--------
0
MOTOROLA 60
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (PK : PC) - 2 PK : PC Push (PC) (SK : SP) - 2 SK : SP Push (CCR) (SK : SP) - 2 SK : SP (PK : PC) + Offset PK : PC If V = 0, branch If V = 1, branch (A) - (B) $00 M Address Mode BSR Branch to Subroutine REL8 Opcode 36 Instruction Operand rr Cycles 10 Condition Codes S MV H EV N Z V C
----------------
BVC2 BVS2 CBA CLR
Branch if Overflow Clear Branch if Overflow Set Compare A to B Clear a Byte in Memory
REL8 REL8 INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH INH IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH IND16, X IND16, Y IND16, Z EXT
B8 B9 371B 05 15 25 1705 1715 1725 1735 3705 3715 27F5 2775 27B7 2705 2715 2725 2735 48 58 68 78 1748 1758 1768 1778 2748 2758 2768 C8 D8 E8 F8 17C8 17D8 17E8 17F8 27C8 27D8 27E8 00 10 20 1700 1710 1720 1730 3700 3710 27F0 2770 2700 2710 2720 2730
rr rr -- ff ff ff gggg gggg gggg hh ll -- -- -- -- -- gggg gggg gggg hh ll ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff gggg gggg gggg hh ll -- -- -- -- gggg gggg gggg hh ll
6, 2 6, 2 2 4 4 4 6 6 6 6 2 2 2 2 2 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 8 8 8 8 8 8 8 2 2 2 2 8 8 8 8
---------------- ---------------- -------- -------- 0 1 0 0
CLRA CLRB CLRD CLRE CLRM CLRW
Clear A Clear B Clear D Clear E Clear AM Clear a Word in Memory
$00 A $00 B $0000 D $0000 E $000000000 AM[35:0] $0000 M : M + 1
-------- -------- -------- -------- -- 0 -- 0 --------
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
--------
CMPA
Compare A to Memory
(A) - (M)
--------

CMPB
Compare B to Memory
(B) - (M)
--------

COM
One's Complement
$FF - (M) M, or M M
--------
0
1
COMA COMB COMD COME COMW
One's Complement A One's Complement B One's Complement E One's Complement Word
$FF - (A) A, or M A $FF - (B) B, or B B $FFFF - (E) E, or E E $FFFF - M : M + 1 M : M + 1, or (M : M + 1) M:M+1
-------- -------- -------- -------- --------

0 0 0 0 0
1 1 1 1 1
One's Complement D $FFFF - (D) D, or D D
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 61
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (D) - (M : M + 1) Address Mode CPD Compare D to Memory IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH IND16, X IND16, Y IND16, Z EXT INH Opcode 88 98 A8 37B8 37C8 37D8 37E8 37F8 2788 2798 27A8 3738 3748 3758 3768 3778 4F 5F 6F 377F 174F 175F 176F 177F 4C 5C 6C 377C 174C 175C 176C 177C 4D 5D 6D 377D 174D 175D 176D 177D 4E 5E 6E 377E 174E 175E 176E 177E 3721 01 11 21 1701 1711 1721 1731 3701 3711 2701 2711 2721 2731 3728 Instruction Operand ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jjkk gggg gggg gggg hhll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll -- ff ff ff gggg gggg gggg hh ll -- -- gggg gggg gggg hh ll -- Cycles 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 2 8 8 8 8 8 8 8 2 2 8 8 8 8 24 Condition Codes S MV H EV N -------- Z V C
CPE
Compare E to Memory
(E) - (M : M + 1)
--------

CPS
Compare Stack Pointer to Memory
(SP) - (M : M + 1)
--------

CPX
Compare IX to Memory
(IX) - (M : M + 1)
--------

CPY
Compare IY to Memory
(IY) - (M : M + 1)
--------

CPZ
Compare IZ to Memory
(IZ) - (M : M + 1)
--------

DAA DEC
Decimal Adjust A Decrement Memory
(A)10 (M) - $01 M
-------- --------

U
--
DECA DECB DECW
Decrement A Decrement B Decrement Memory Word
(A) - $01 A (B) - $01 B (M : M + 1) - $0001 M:M+1
-------- -------- --------

-- -- --
EDIV
Extended Unsigned Integer Divide
(E : D) / (IX) Quotient IX Remainder D
--------

MOTOROLA 62
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (E : D) / (IX) Quotient IX Remainder D (E) (D) E : D (E) (D) E : D (A) (M) A Address Mode EDIVS Extended Signed Integer Divide Extended Unsigned Multiply Extended Signed Multiply Exclusive OR A INH Opcode 3729 Instruction Operand -- Cycles 38 Condition Codes S MV H EV N -------- Z V C
EMUL EMULS EORA
INH INH IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH INH INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH IND16, X IND16, Y IND16, Z EXT
3725 3726 44 54 64 74 1744 1754 1764 1774 2744 2754 2764 C4 D4 E4 F4 17C4 17D4 17E4 17F4 27C4 27D4 27E4 84 94 A4 37B4 37C4 37D4 37E4 37F4 2784 2794 27A4 3734 3744 3754 3764 3774 372B 3727 372A 03 13 23 1703 1713 1723 1733 3703 3713 2703 2713 2723 2733
-- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll -- -- -- ff ff ff gggg gggg gggg hh ll -- -- gggg gggg gggg hh ll
10 8 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 22 8 22 8 8 8 8 8 8 8 2 2 8 8 8 8
-------- -------- --------

-- -- 0
--
EORB
Exclusive OR B
(B) (M) B
--------
0
--
EORD
Exclusive OR D
(D) (M : M + 1) D
--------
0
--
EORE
Exclusive OR E
(E) (M : M + 1) E
--------
0
--
FDIV FMULS IDIV INC
Fractional Unsigned Divide Fractional Signed Multiply Integer Divide Increment Memory
(D) / (IX) IX Remainder D (E) (D) E : D[31:1] 0 D[0] (D) / (IX) IX Remainder D (M) + $01 M
---------- --------

0
--
---------- --------
INCA INCB INCW
Increment A Increment B Increment Memory Word
(A) + $01 A (B) + $01 B (M : M + 1) + $0001 M:M+1
-------- -------- --------

-- -- --
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 63
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description ea PK : PC Address Mode JMP Jump EXT20 IND20, X IND20, Y IND20, Z EXT20 IND20, X IND20, Y IND20, Z REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 Opcode 7A 4B 5B 6B FA 89 99 A9 3784 3785 3787 3791 378C 378E 3782 378F 3783 378D 378B 3790 3786 378A 3780 3781 27F9 Instruction Operand zb hh ll zg gggg zg gggg zg gggg zb hh ll zg gggg zg gggg zg gggg rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr Cycles 6 8 8 8 10 12 12 12 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6 6 10 Condition Codes S MV H EV N Z V C
----------------
JSR
Jump to Subroutine
Push (PC) (SK : SP) - $0002 SK : SP Push (CCR) (SK : SP) - $0002 SK : SP ea PK : PC If C = 0, branch If C = 1, branch If Z = 1, branch If EV = 1, branch If N V = 0, branch If Z ' (N V) = 0, branch If C ' Z = 0, branch If Z ' (N V) = 1, branch If C ' Z = 1, branch If N V = 1, branch If N = 1, branch If MV = 1, branch If Z = 0, branch If N = 0, branch If 1 = 1, branch If 1 = 0, branch Push (PC) (SK : SP) - 2 SK : SP Push (CCR) (SK : SP) - 2 SK : SP (PK : PC) + Offset PK : PC If V = 0, branch If V = 1, branch (M) A
----------------
LBCC2 LBCS2 LBEQ2 LBEV2 LBGE2 LBGT2 LBHI 2 LBLE2 LBLS2 LBLT2 LBMI2 LBMV2 LBNE2 LBPL2 LBRA LBRN LBSR
Long Branch if Carry Clear Long Branch if Carry Set Long Branch if Equal to Zero Long Branch if EV Set Long Branch if Greater Than or Equal to Zero Long Branch if Greater Than Zero Long Branch if Higher Long Branch if Less Than or Equal to Zero Long Branch if Lower or Same Long Branch if Less Than Zero Long Branch if Minus Long Branch if MV Set Long Branch if Not Equal to Zero Long Branch if Plus Long Branch Always Long Branch Never Long Branch to Subroutine
---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ----------------
LBVC2 LBVS2 LDAA
Long Branch if Overflow Clear Long Branch if Overflow Set Load A
REL16 REL16 IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z
3788 3789 45 55 65 75 1745 1755 1765 1775 2745 2755 2765
rrrr rrrr ff ff ff ii gggg gggg gggg hh ll -- -- --
6, 4 6, 4 6 6 6 2 6 6 6 6 6 6 6
---------------- ---------------- -------- 0 --
MOTOROLA 64
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (M) B Address Mode LDAB Load B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT EXT EXT Opcode C5 D5 E5 F5 17C5 17D5 17E5 17F5 27C5 27D5 27E5 85 95 A5 37B5 37C5 37D5 37E5 37F5 2785 2795 27A5 3735 3745 3755 3765 3775 2771 27B0 Instruction Operand ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll hh ll -- Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 8 8 Condition Codes S MV H EV N -------- Z V 0 C
LDD
Load D
(M : M + 1) D
--------
0
--
LDE
Load E
(M : M + 1) E
--------
0
--
LDED LDHI
Load Concatenated E and D Initialize H and I
(M : M + 1) E (M + 2 : M + 3) D (M : M + 1)X H R (M : M + 1)Y I R (M : M + 1) SP
---------------- ----------------
LDS
Load SP
IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IMM16 IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH
CF DF EF 17CF 17DF 17EF 17FF 37BF CC DC EC 37BC 17CC 17DC 17EC 17FC CD DD ED 37BD 17CD 17DD 17ED 17FD CE DE EE 37BE 17CE 17DE 17EE 17FE 27F1
ff ff ff gggg gggg gggg hh ll jj kk ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll --
6 6 6 6 6 6 6 4 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 4, 20
--------
0
--
LDX
Load IX
(M : M + 1) IX
--------
0
--
LDY
Load IY
(M : M + 1) IY
--------
0
--
LDZ
Load IZ
(M : M + 1) IZ
--------
0
--
LPSTOP
Low Power Stop
If S then STOP else NOP
----------------
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 65
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description Address Mode LSR Logical Shift Right IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH Opcode 0F 1F 2F 170F 171F 172F 173F 370F Instruction Operand ff ff ff gggg gggg gggg hh ll -- Cycles 8 8 8 8 8 8 8 2 Condition Codes S MV H EV N -------- 0 Z V C
LSRA
Logical Shift Right A
--------
0
LSRB
Logical Shift Right B
INH
371F
--
2
--------
0
LSRD
Logical Shift Right D
INH
27FF
--
2
--------
0
LSRE
Logical Shift Right E
INH
277F
--
2
--------
0
LSRW
Logical Shift Right Word
IND16, X IND16, Y IND16, Z EXT (HR) (IR) E : D (AM) + (E : D) AM Qualified (IX) IX Qualified (IY) IY (HR) IZ (M : M + 1)X HR (M : M + 1)Y IR (M1) M2 IMM8
270F 271F 272F 273F 7B
gggg gggg gggg hh ll xoyo
8 8 8 8 12
--------
0
MAC
Multiply and Accumulate Signed 16-Bit Fractions
--
--
----
--
MOVB
Move Byte
IXP to EXT EXT to IXP EXT to EXT IXP to EXT EXT to IXP EXT to EXT INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH IND16, X IND16, Y IND16, Z EXT INH
30 32 37FE 31 33 37FF 3724 02 12 22 1702 1712 1722 1732 3702 3712 27F2 2772 2702 2712 2722 2732 274C
ff hh ll ff hh ll hh ll hh ll ff hh ll ff hh ll hh ll hh ll -- ff ff ff gggg gggg gggg hh ll -- -- -- -- gggg gggg gggg hh ll --
8 8 10 8 8 10 10 8 8 8 8 8 8 8 2 2 2 2 8 8 8 8 2
--------
0
--
MOVW
Move Word
(M : M + 11) M : M + 12
--------
0
--
MUL NEG
Multiply Negate Memory
(A) (B) D $00 - (M) M
-------------- --------

NEGA NEGB NEGD NEGE NEGW
Negate A Negate B Negate D Negate E Negate Memory Word
$00 - (A) A $00 - (B) B $0000 - (D) D $0000 - (E) E $0000 - (M : M + 1) M:M+1
-------- -------- -------- -------- --------

NOP
Null Operation
--
----------------
MOTOROLA 66
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (A) ' (M) A Address Mode ORAA OR A IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IMM16 INH Opcode 47 57 67 77 1747 1757 1767 1777 2747 2757 2767 C7 D7 E7 F7 17C7 17D7 17E7 17F7 27C7 27D7 27E7 87 97 A7 37B7 37C7 37D7 37E7 37F7 2787 2797 27A7 3737 3747 3757 3767 3777 373B 3708 Instruction Operand ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll jj kk -- Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 4 4 Condition Codes S MV H EV N -------- Z V 0 C --
ORAB
OR B
(B) ' (M) B
--------
0
--
ORD
OR D
(D) ' (M : M + 1) D
--------
0
--
ORE
OR E
(E) ' (M : M + 1) E
--------
0
--
ORP 1 PSHA
OR Condition Code Register Push A
(CCR) ' IMM16 CCR (SK : SP) + $0001 SK : SP Push (A) (SK : SP) - $0002 SK : SP (SK : SP) + $0001 SK : SP Push (B) (SK : SP) - $0002 SK : SP For mask bits 0 to 7: If mask bit set Push register (SK : SP) - 2 SK : SP

----------------
PSHB
Push B
INH
3718
--
4
----------------
PSHM
Push Multiple Registers Mask bits: 0=D 1=E 2 = IX 3 = IY 4 = IZ 5=K 6 = CCR 7 = (Reserved)
IMM8
34
ii
4 + 2N
----------------
N= number of iterations
PSHMAC PULA
Push MAC Registers Pull A
MAC Registers Stack (SK : SP) + $0002 SK : SP Pull (A) (SK : SP) - $0001 SK : SP (SK : SP) + $0002 SK : SP Pull (B) (SK : SP) - $0001 SK : SP
INH INH
27B8 3709
-- --
14 6
---------------- ----------------
PULB
Pull B
INH
3719
--
6
----------------
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 67
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description Address Mode PULM
1
Instruction Opcode 35 Operand ii Cycles 4+2(N+1) N= number of iterations
Condition Codes S MV H EV N Z V C
Pull Multiple Registers Mask bits: 0 = CCR[15:4] 1=K 2 = IZ 3 = IY 4 = IX 5=E 6=D 7 = (Reserved)
For mask bits 0 to 7: If mask bit set (SK : SP) + 2 SK : SP Pull register
IMM8
PULMAC RMAC
Pull MAC State Repeating Multiply and Accumulate Signed 16-Bit Fractions
Stack MAC Registers Repeat until (E) < 0 (AM) + (H) (I) AM Qualified (IX) IX; Qualified (IY) IY; (M : M + 1)X H; (M : M + 1) I
Y
INH IMM8
27B9 FB
-- xoyo
16 6 + 12 per iteration
---------------- -- -- --------
(E) - 1 E Until (E) < $0000 ROL Rotate Left IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH 0C 1C 2C 170C 171C 172C 173C 370C ff ff ff gggg gggg gggg hh ll -- 8 8 8 8 8 8 8 2 --------
ROLA
Rotate Left A
--------

ROLB
Rotate Left B
INH
371C
--
2
--------

ROLD
Rotate Left D
INH
27FC
--
2
--------

ROLE
Rotate Left E
INH
277C
--
2
--------

ROLW
Rotate Left Word
IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH
270C 271C 272C 273C 0E 1E 2E 170E 171E 172E 173E 370E
gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll --
8 8 8 8 8 8 8 8 8 8 8 2
--------

ROR
Rotate Right Byte
--------

RORA
Rotate Right A
--------

RORB
Rotate Right B
INH
371E
--
2
--------

RORD
Rotate Right D
INH
27FE
--
2
--------

RORE
Rotate Right E
INH
277E
--
2
--------

MOTOROLA 68
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description Address Mode RORW Rotate Right Word IND16, X IND16, Y IND16, Z EXT (SK : SP) + 2 SK : SP Pull CCR (SK : SP) + 2 SK : SP Pull PC (PK : PC) - 6 PK : PC (SK : SP) + 2 SK : SP Pull PK (SK : SP) + 2 SK : SP Pull PC (PK : PC) - 2 PK : PC (A) - (B) A (A) - (M) - C A INH Opcode 270E 271E 272E 273E 2777 Instruction Operand gggg gggg gggg hh ll -- Cycles 8 8 8 8 12 Condition Codes S MV H EV N -------- Z V C
RTI3
Return from Interrupt

RTS4
Return from Subroutine
INH
27F7
--
12
----------------
SBA SBCA
Subtract B from A Subtract with Carry from A
INH IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z
370A 42 52 62 72 1742 1752 1762 1772 2742 2752 2762 C2 D2 E2 F2 17C2 17D2 17E2 17F2 27C2 27D2 27E2 82 92 A2 37B2 37C2 37D2 37E2 37F2 2782 2792 27A2 3732 3742 3752 3762 3772 2779 4A 5A 6A 174A 175A 176A 177A 274A 275A 276A
-- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll -- ff ff ff gggg gggg gggg hh ll -- -- --
2 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 2 4 4 4 6 6 6 6 4 4 4
-------- --------

SBCB
Subtract with Carry from B
(B) - (M) - C B
--------

SBCD
Subtract with Carry from D
(D) - (M : M + 1) - C D
--------

SBCE
Subtract with Carry from E
(E) - (M : M + 1) - C E
--------

SDE STAA
Subtract D from E Store A
(E) - (D) E (A) M
-------- --------

0
--
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 69
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (B) M Address Mode STAB Store B IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND16, X IND16, Y IND16, Z EXT EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z Opcode CA DA EA 17CA 17DA 17EA 17FA 27CA 27DA 27EA 8A 9A AA 37CA 37DA 37EA 37FA 278A 279A 27AA 374A 375A 376A 377A 2773 8F 9F AF 178F 179F 17AF 17BF 8C 9C AC 178C 179C 17AC 17BC 8D 9D AD 178D 179D 17AD 17BD 8E 9E AE 178E 179E 17AE 17BE 40 50 60 70 1740 1750 1760 1770 2740 2750 2760 Instruction Operand ff ff ff gggg gggg gggg hh ll -- -- -- ff ff ff gggg gggg gggg hh ll -- -- -- gggg gggg gggg hh ll hh ll ff ff ff gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll ff ff ff ii gggg gggg gggg hh ll -- -- -- Cycles 4 4 4 6 6 6 6 4 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 8 4 4 4 6 6 6 6 4 4 4 6 6 6 6 4 4 4 6 6 6 6 4 4 4 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 Condition Codes S MV H EV N -------- Z V 0 C --
STD
Store D
(D) M : M + 1
--------
0
--
STE
Store E
(E) M : M + 1
--------
0
--
STED STS
Store Concatenated D and E Store Stack Pointer
(E) M : M + 1 (D) M + 2 : M + 3 (SP) M : M + 1
---------------- -------- 0 --
STX
Store IX
(IX) M : M + 1
--------
0
--
STY
Store IY
(IY) M : M + 1
--------
0
--
STZ
Store Z
(IZ) M : M + 1
--------
0
--
SUBA
Subtract from A
(A) - (M) A
--------

MOTOROLA 70
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description (B) - (M) B Address Mode SUBB Subtract from B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH Opcode C0 D0 E0 F0 17C0 17D0 17E0 17F0 27C0 27D0 27E0 80 90 A0 37B0 37C0 37D0 37E0 37F0 2780 2790 27A0 3730 3740 3750 3760 3770 3720 Instruction Operand ff ff ff ii gggg gggg gggg hh ll -- -- -- ff ff ff jj kk gggg gggg gggg hh ll -- -- -- jj kk gggg gggg gggg hh ll -- Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 16 Condition Codes S MV H EV N -------- Z V C
SUBD
Subtract from D
(D) - (M : M + 1) D
--------

SUBE
Subtract from E
(E) - (M : M + 1) E
--------

SWI
Software Interrupt
(PK : PC) + $0002 PK : PC Push (PC) (SK : SP) - $0002 SK : SP Push (CCR) (SK : SP) - $0002 SK : SP $0 PK SWI Vector PC If B7 = 1 then $FF A else $00 A (A) B (A[7:0]) CCR[15:8] (B) A (B[3:0]) EK (B[3:0]) SK (B[3:0]) XK (B[3:0]) YK (B[3:0]) ZK (D) E (D[15:8]) X MASK (D[7:0]) Y MASK (D) CCR[15:4] (E) D (E) AM[31:16] (D) AM[15:0] AM[35:32] = AM31 (EK) B[3:0] $0 B[7:4] (E) AM[31:16] $00 AM[15:0] AM[35:32] = AM31 Rounded (AM) Temp If (SM * (EV ' MV)) then Saturation Value E else Temp[31:16] E
----------------
SXT
Sign Extend B into A
INH
27F8
--
2
--------
----
TAB TAP TBA TBEK TBSK TBXK TBYK TBZK TDE TDMSK TDP1 TED TEDM
Transfer A to B Transfer A to CCR Transfer B to A Transfer B to EK Transfer B to SK Transfer B to XK Transfer B to YK Transfer B to ZK Transfer D to E Transfer D to XMSK : YMSK Transfer D to CCR Transfer E to D Transfer E and D to AM[31:0] Sign Extend AM Transfer EK to B Transfer E to AM[31:16] Sign Extend AM Clear AM LSB Transfer Rounded AM to E
INH INH INH INH INH INH INH INH INH INH INH INH INH
3717 37FD 3707 27FA 379F 379C 379D 379E 277B 372F 372D 27FB 27B1
-- -- -- -- -- -- -- -- -- -- -- -- --
2 4 2 2 2 2 2 2 2 2 4 2 4
-------- --------

0 0
-- --
---------------- ---------------- ---------------- ---------------- ---------------- -------- 0 -- ---------------- 0 --
-------- -- 0 -- 0
--------
TEKB TEM
INH INH
27BB 27B2
-- --
2 4
---------------- -- 0 -- 0 --------
TMER
INH
27B4
--
6
--
--
----
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 71
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description If (SM * (EV ' MV)) then Saturation Value E else AM[31:16] E AM[35:32] IX[3:0] AM35 IX[15:4] AM[31:16] E AM[15:0] D (CCR[15:8]) A (CCR) D (SK) B[3:0] $0 B[7:4] (M) - $00 Address Mode TMET Transfer Truncated AM to E Transfer AM to IX : E : D INH Opcode 27B5 Instruction Operand -- Cycles 2 Condition Codes S MV H EV N -------- Z V C
----
TMXED
INH
27B3
--
6
----------------
TPA TPD TSKB TST
Transfer CCR to A Transfer CCR to D Transfer SK to B Test Byte Zero or Minus
INH INH INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH IND16, X IND16, Y IND16, Z EXT INH INH INH INH INH INH INH INH INH INH INH INH INH INH INH
37FC 372C 37AF 06 16 26 1706 1716 1726 1736 3706 3716 27F6 2776 2706 2716 2726 2736 274F 275F 276F 37AC 374E 275C 276C 37AD 375E 274D 276D 37AE 376E 274E 275E
-- -- -- ff ff ff gggg gggg gggg hh ll -- -- -- -- gggg gggg gggg hh ll -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
2 2 2 6 6 6 6 6 6 6 2 2 2 2 6 6 6 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
---------------- ---------------- ---------------- -------- 0 0
TSTA TSTB TSTD TSTE TSTW
Test A for Zero or Minus Test B for Zero or Minus Test D for Zero or Minus Test E for Zero or Minus Test for Zero or Minus Word
(A) - $00 (B) - $00 (D) - $0000 (E) - $0000 (M : M + 1) - $0000
-------- -------- -------- -------- --------

0 0 0 0 0
0 0 0 0 0
TSX TSY TSZ TXKB TXS TXY TXZ TYKB TYS TYX TYZ TZKB TZS TZX TZY
Transfer SP to IX Transfer SP to IY Transfer SP to IZ Transfer XK to B Transfer IX to SP Transfer IX to IY Transfer IX to IZ Transfer YK to B Transfer IY to SP Transfer IY to IX Transfer IY to IZ Transfer ZK to B Transfer IZ to SP Transfer IZ to IX Transfer IZ to IY
(SK : SP) + $0002 XK : IX (SK : SP) + $0002 YK : IY (SK : SP) + $0002 ZK : IZ (XK) B[3:0] $0 B[7:4] (XK : IX) - $0002 SK : SP (XK : IX) YK : IY (XK : IX) ZK : IZ (YK) B[3:0] $0 B[7:4] (YK : IY) - $0002 SK : SP (YK : IY) XK : IX (YK : IY) ZK : IZ (ZK) B[3:0] $0 B[7:4] (ZK : IZ) - $0002 SK : SP (ZK : IZ) XK : IX (ZK : IZ) ZK : IY
---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ----------------
MOTOROLA 72
MC68HC916X1 MC68HC916X1TS/D
Table 35 Instruction Set Summary (Continued)
Mnemonic Operation Description Address Mode WAI XGAB XGDE XGDX XGDY XGDZ XGEX XGEY XGEZ Wait for Interrupt Exchange A with B Exchange D with E Exchange D with IX Exchange D with IY Exchange D with IZ Exchange E with IX Exchange E with IY Exchange E with IZ WAIT (A) (B) (D) (E) (D) (IX) (D) (IY) (D) (IZ) (E) (IX) (E) (IY) (E) (IZ) INH INH INH INH INH INH INH INH INH Opcode 27F3 371A 277A 37CC 37DC 37EC 374C 375C 376C Instruction Operand -- -- -- -- -- -- -- -- -- Cycles 8 2 2 2 2 2 2 2 2 Condition Codes S MV H EV N Z V C
---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ---------------- ----------------
1. CCR[15:4] change according to results of operation. The PK field is not affected. 2. Cycle times for conditional branches are shown in "taken, not taken" order. 3. CCR[15:0] change according to copy of CCR pulled from stack. 4. PK field changes according to state pulled from stack. The rest of the CCR is not affected.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 73
Table 36 Instruction Set Abbreviations and Symbols
A -- Accumulator A AM -- Accumulator M B -- Accumulator B CCR -- Condition code register D -- Accumulator D E -- Accumulator E EK -- Extended addressing extension field IR -- MAC multiplicand register HR -- MAC multiplier register IX -- Index register X IY -- Index register Y IZ -- Index register Z K -- Address extension register PC -- Program counter PK -- Program counter extension field SK -- Stack pointer extension field SL -- Multiply and accumulate sign latch SP -- Stack pointer XK -- Index register X extension field YK -- Index register Y extension field ZK -- Index register Z extension field XMSK -- Modulo addressing index register X mask YMSK -- Modulo addressing index register Y mask S -- Stop disable control bit MV -- AM overflow indicator H -- Half carry indicator EV -- AM extended overflow indicator N -- Negative indicator Z -- Zero indicator V -- Two's complement overflow indicator C -- Carry/borrow indicator IP -- Interrupt priority field SM -- Saturation mode control bit PK -- Program counter extension field -- -- Bit not affected -- Bit changes as specified 0 -- Bit cleared 1 -- Bit set M -- Memory location used in operation R -- Result of operation S -- Source data X -- Register used in operation M -- Address of one memory byte M +1 -- Address of byte at M + $0001 M : M + 1 -- Address of one memory word (...)X -- Contents of address pointed to by IX (...)Y -- Contents of address pointed to by IY (...)Z -- Contents of address pointed to by IZ E, X -- IX with E offset E, Y -- IY with E offset E, Z -- IZ with E offset EXT -- Extended EXT20 -- 20-bit extended IMM8 -- 8-bit immediate IMM16 -- 16-bit immediate IND8, X -- IX with unsigned 8-bit offset IND8, Y -- IY with unsigned 8-bit offset IND8, Z -- IZ with unsigned 8-bit offset IND16, X -- IX with signed 16-bit offset IND16, Y -- IY with signed 16-bit offset IND16, Z -- IZ with signed 16-bit offset IND20, X -- IX with signed 20-bit offset IND20, Y -- IY with signed 20-bit offset IND20, Z -- IZ with signed 20-bit offset INH -- Inherent IXP -- Post-modified indexed REL8 -- 8-bit relative REL16 -- 16-bit relative b -- 4-bit address extension ff -- 8-bit unsigned offset gggg -- 16-bit signed offset hh -- High byte of 16-bit extended address ii -- 8-bit immediate data jj -- High byte of 16-bit immediate data kk -- Low byte of 16-bit immediate data ll -- Low byte of 16-bit extended address mm -- 8-bit mask mmmm -- 16-bit mask rr -- 8-bit unsigned relative offset rrrr -- 16-bit signed relative offset xo -- MAC index register X offset yo -- MAC index register Y offset z -- 4-bit zero extension + -- Addition - -- Subtraction or negation (two's complement) -- Multiplication / -- Division > -- Greater < -- Less = -- Equal -- Equal or greater -- Equal or less -- Not equal * -- AND ' -- Inclusive OR (OR) -- Exclusive OR (EOR) NOT -- Complementation : -- Concatenation -- Transferred -- Exchanged -- Sign bit; also used to show tolerance -- Sign extension % -- Binary value $ -- Hexadecimal value
MOTOROLA 74
MC68HC916X1 MC68HC916X1TS/D
4.7 Exceptions An exception is an event that preempts normal instruction process. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. Each exception has an assigned vector that points to an associated handler routine. Exception processing includes all operations required to transfer control to a handler routine, but does not include execution of the handler routine itself. Keep the distinction between exception processing and execution of an exception handler in mind while reading this section. 4.7.1 Exception Vectors An exception vector is the address of a routine that handles an exception. Exception vectors are contained in a data structure called the exception vector table, which is located in the first 512 bytes of bank 0. Refer to Table 37 for the exception vector table. All vectors except the reset vector consist of one word and reside in data space. The reset vector consists of four words that reside in program space. There are 52 predefined or reserved vectors, and 200 user-defined vectors. Each vector is assigned an 8-bit number. Vector numbers for some exceptions are generated by external devices; others are supplied by the processor. There is a direct mapping of vector number to vector table address. The processor left shifts the vector number one place (multiplies by two) to convert it to an address. Table 37 Exception Vector Table
Vector Number 0 Vector Address 0000 0002 0004 0006 4 5 6 7 8 9-E F 10 11 12 13 14 15 16 17 18 19 - 37 38 - FF 0008 000A 000C 000E 0010 0012 - 001C 001E 0020 0022 0024 0026 0028 002A 002C 002E 0030 0032 - 006E 0070 - 01FE Address Space P P P P D D D D D D D D D D D D D D D D D D Type of Exception Reset -- Initial ZK, SK, and PK Reset -- Initial PC Reset -- Initial SP Reset -- Initial IZ (Direct Page) Breakpoint Bus Error Software Interrupt Illegal Instruction Division by Zero Unassigned, Reserved Uninitialized Interrupt Unassigned, Reserved Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Spurious Interrupt Unassigned, Reserved User-Defined Interrupts
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 75
4.7.2 Exception Stack Frame During exception processing, the contents of the program counter and condition code register are stacked at a location pointed to by SK:SP. Unless it is altered during exception processing, the stacked PK:PC value is the address of the next instruction in the current instruction stream, plus $0006. Figure 12 shows the exception stack frame.
High Address Condition Code Register High Address Program Counter
SP After Exception Stacking SP Before Exception Stacking
Figure 12 Exception Stack Frame Format 4.7.3 Exception Processing Sequence Exception processing is performed in four phases. A. Priority of all pending exceptions is evaluated, and the highest priority exception is processed first. B. Processor state is stacked, then the CCR PK extension field is cleared. C. An exception vector number is acquired and converted to a vector address. D. The content of the vector address is loaded into the PC, and the processor jumps to the exception handler routine. There are variations within each phase for differing types of exceptions. However, all vectors but the reset vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located within bank 0 or vectors must point to a jump table. 4.7.4 Types of Exceptions Exceptions can be either internally or externally generated. External exceptions, which are defined as asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET). Internal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception. 4.7.4.1 Asynchronous Exceptions Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing is synchronized. For all asynchronous exceptions but RESET, exception processing begins at the first instruction boundary following recognition of an exception. Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than reset, is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value to resume execution of the interrupted instruction stream. 4.7.4.2 Synchronous Exceptions Synchronous exception processing is part of an instruction definition. Exception processing for synchronous exceptions is always completed, and the first instruction of the handler routine is always executed, before interrupts are detected.
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Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to the address of the instruction that causes the exception plus $0006. Because RTI always subtracts $0006 upon return, the stacked PK : PC must be adjusted by the instruction that caused the exception so that execution resumes with the following instruction. For this reason, $0002 is added to the PK : PC value before it is stacked. 4.7.5 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation. Asynchronous exceptions have higher priorities than synchronous exceptions. Exception processing for multiple exceptions is completed by priority, from highest to lowest. Priority governs the order in which exception processing occurs, not the order in which exception handlers are executed. Unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of all exception handler routines is guaranteed to execute before another exception is processed. Because interrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt handler are executed before other interrupts are sensed. Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous exception are processed before the first instruction of that exception's handler routine. The converse is not true. If an interrupt occurs during bus error exception processing, for example, the first instruction of the exception handler is executed before interrupts are sensed. This permits the exception handler to mask interrupts during execution. 4.7.6 RTI Instruction The return-from-interrupt instruction (RTI) must be the last instruction in all exception handlers except the RESET handler. RTI pulls the exception stack frame that was pushed onto the system stack during exception processing, and restores processor state. Normal program flow resumes at the address of the instruction that follows the last instruction executed before exception processing began. RTI is not used in the RESET handler because RESET initializes the stack pointer and does not create a stack frame.
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5 Analog-to-Digital Converter Module
The analog-to-digital converter module (ADC) is a unipolar, successive-approximation converter with eight modes of operation. It has selectable 8- or 10-bit resolution. Monotonicity is guaranteed in both modes. ADC module conversion functions can be grouped into three basic subsystems: an analog front end, a digital control section, and result storage. In addition, the six analog inputs can be used as a general-purpose digital input (port ADA), provided signals are within logic level specification. Figure 13 shows a block diagram of the ADC converter module. 5.1 Analog Subsystem The analog front end consists of a multiplexer, a buffer amplifier, a resistor-capacitor array, and a high-gain comparator. The multiplexer selects one of six internal or six external signal sources for conversion. The buffer amplifier protects the input channel from the relatively large capacitance of the resistor capacitor (RC) array. The RC array performs two functions: it acts as a sample/hold circuit, and it provides the digital-to-analog comparison output necessary for successive approximation conversion. The comparator indicates whether each successive output of the RC array is higher or lower than the sampled input. 5.2 Digital Control Subsystem The digital control section includes conversion sequence control logic, channel and reference select logic, a successive approximation register, eight result registers, a port data register, and control/ status registers. It controls the multiplexer and the output of the RC array during the sample and conversion periods, stores the results of comparison in the successive-approximation register, and transfers the result to a result register. 5.3 Bus Interface Subsystem The ADC bus interface unit contains logic necessary to interface the ADC to the intermodule bus. The ADC is designed to act as a slave device on the bus. The interface must respond with appropriate bus cycle termination signals and supply appropriate interface timing to the other submodules.
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RC DAC ARRAY AND COMPARATOR
ANALOG MUX AND SAMPLE BUFFER AMP RESERVED RESERVED RESERVED RESERVED V RH V RL (V RH-VRL )/2 RESERVED
AN7 AN6
V RH V RL
REFERENCE
SAR MODE AND TIMING CONTROL RESULT 0 RESULT 1 RESULT 2 RESULT 3 RESULT 4 RESULT 5 RESULT 6 RESULT 7
AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0
INTERNAL CONNECTIONS
PORT ADA DATA REGISTER PADA6
PADA7
V DDA V SSA
SUPPLY
CLK SELECT/ PRESCALE
ADC BUS INTERFACE UNIT
INTERMODULE BUS (IMB)
ADC BLOCK 6CHAN
Figure 13 Analog-to-Digital Converter Block Diagram
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5.4 ADC Address Map Table 38 shows the ADC address map. Table 38 ADC Address Map
Address $YFF700
1
15
8
7
0
ADC MODULE CONFIGURATION REGISTER (ADCMCR) ADC TEST REGISTER (ADCTEST) RESERVED PORT ADA DATA (PORTADA) RESERVED ADC CONTROL REGISTER 0 (ADCTL0) ADC CONTROL REGISTER 1 (ADCTL1) ADC STATUS REGISTER (ADSTAT) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 0 (RJURR0) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 1 (RJURR1) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 2 (RJURR2) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 3 (RJURR3) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 4 (RJURR4) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 5 (RJURR5) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 6 (RJURR6) RIGHT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 7 (RJURR7) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 0 (LJSRR0) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 1 (LJSRR1) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 2 (LJSRR2) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 3 (LJSRR3) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 4 (LJSRR4) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 5 (LJSRR5) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 6 (LJSRR6) LEFT-JUSTIFIED SIGNED ADC RESULT REGISTER 7 (LJSRR7) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 0 (LJURR0) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 1 (LJURR1) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 2 (LJURR2) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 3 (LJURR3) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 4 (LJURR4) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 5 (LJURR5) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 6 (LJURR6) LEFT-JUSTIFIED UNSIGNED ADC RESULT REGISTER 7 (LJURR7)
$YFF702 $YFF704 $YFF706 $YFF708 $YFF70A $YFF70C $YFF70E $YFF710 $YFF712 $YFF714 $YFF716 $YFF718 $YFF71A $YFF71C $YFF71E $YFF720 $YFF722 $YFF724 $YFF726 $YFF728 $YFF72A $YFF72C $YFF72E $YFF730 $YFF732 $YFF734 $YFF736 $YFF738 $YFF73A $YFF73C $YFF73E
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIMCR.
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5.5 ADC Registers The following section provides a summary of ADC registers and their contents. ADCMCR -- ADC Module Configuration Register
STOP 1 15 14 FRZ[1:0] 13 12 11 NOT USED 10 9 8 SUPV 0 7 6 5 4 NOT USED 3 2
$YFF700
1 0
RESET:
0
0
The ADCMCR is used to initialize the ADC. STOP -- STOP Mode 0 = Normal operation 1 = Low-power operation STOP places the ADC in low-power state by disabling the ADC clock and powering down the analog circuitry. Setting STOP aborts any conversion in progress. STOP is set to logic level one at reset, and may be cleared to logic level zero by the CPU. Clearing STOP enables normal ADC operation. However, because analog circuitry bias current has been turned off, there is a period of recovery before output stabilization. FRZ[1:0] -- FREEZE Assertion Response The FRZ field is used to determine ADC response to assertion of the IMB FREEZE signal. Table 39 shows possible responses. Table 39 FREEZE Assertion Response
FRZ[1:0] 00 01 10 11 Reserved Finish conversion, then freeze Freeze immediately Response Ignore FREEZE
SUPV -- Supervisor/Unrestricted Data Space This bit has no effect because the CPU16 always operates in the supervisor mode. ADTEST -- ADC Test Register ADTEST is used during factory test of the ADC. PORTADA -- Port ADA Data Register
15 RESET: 14 13 12 NOT USED 11 10 9 8 7 6 5 4 3 2
$YFF702
$YFF706
PADA7 PADA6 PADA5 PADA4 PADA3 PADA2 PADA1 PADA0 0 0 REFLECTS STATE OF THE INPUT PINS 1 0
Port ADA is an input port that shares pins with the A/D converter inputs. PADA[7:6] -- Port ADA Data Pins PADA[7:6] digital inputs to the ADC module are internally connected to VSSA. The corresponding bits in PORTADA will read zero at all times.
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PADA[5:0] -- Port ADA Data Pins A read of PADA[5:0] returns the logic level of the port ADA pins. If an input is not at an appropriate logic level (i.e. outside the defined levels), the read is indeterminate. Use of a port ADA pin for digital input does not preclude use as an analog input. ADCTL0 -- A/D Control Register 0
15 RESET: 14 13 12 NOT USED 11 10 9 8 RES10 0 7 6 STS[1:0] 5 4 3 PRS[4:0] 0 2
$YFF70A
1 0
0
0
0
0
1
1
ADCTL0 is used to select ADC clock source and to set up prescaling. Writes to it have immediate effect. RES10 -- 10-Bit Resolution 0 = 8-bit resolution 1 = 10-bit resolution Conversion results are appropriately aligned in result registers to reflect conversion status. STS[1:0] -- Sample Time Select Total conversion time depends on initial sample time, transfer time, final sample time, and resolution time. Initial sample time is fixed at two clocks. Transfer time is fixed at two clocks. Resolution time is fixed at 10 ADC clock cycles for an 8-bit conversion and 12 ADC clock cycles for a 10-bit conversion. Final sample time depends on the STS[1:0] field. Refer to Table 40.
Table 40 Sample Time Select Field
STS[1:0] 00 01 10 11 Sample Time 2 A/D Clock Periods 4 A/D Clock Periods 8 A/D Clock Periods 16 A/D Clock Periods
PRS[4:0] -- Prescaler Rate Selection Field The ADC clock is generated from the system clock using a modulo counter and a divide-by-two circuit. The binary value of this field is the counter modulus. System clock is divided by the PRS[4:0] value plus one, then sent to the divide-by-two circuit. Refer to Table 41.
Table 41 Prescaler Rate Selection Field
PRS[4:0] 00000 00001 00010 ... 11101 11110 11111 Divisor Value 4 4 6 ... 60 62 64
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ADCTL1 -- A/D Control Register 1
15 RESET: 14 13 12 NOT USED 11 10 9 8 7 SCAN 0 6 MULT 0 5 S8CM 0 4 CD 0 3 CC 0 2
$YFF70C
CB 0 1 CA 0 0
ADCTL1 is used to initiate an A/D conversion and to select conversion modes and a conversion channel. It can be written or read at any time. A write to ADCTL1 initiates a conversion sequence. If a conversion sequence is already in progress, a write to ADCTL1 aborts it and resets the SCF and CCF flags in the ADC status register. SCAN -- Scan Mode Selection Bit 0 = Single conversion sequence 1 = Continuous conversion Length of conversion sequence(s) is determined by S8CM. MULT -- Multichannel Conversion Bit 0 = Conversion sequence(s) run on single channel (channel selected via [CD:CA]) 1 = Sequential conversion of a block of four or eight channels (block selected via [CD:CA]) Length of conversion sequence(s) is determined by S8CM. S8CM -- Select Eight-Conversion Sequence Mode 0 = Four-conversion sequence 1 = Eight-conversion sequence This bit determines the number of conversions in a conversion sequence. [CD:CA] -- Channel Selection Field The bits in this field are used to select an input or block of inputs for A/D conversion. Table 42 summarizes the operation of S8CM and [CD:CA] when MULT is cleared (single channel mode). Number of conversions per channel is determined by SCAN.
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Table 42 Single-Channel Conversions
S8CM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input AN0 AN1 AN2 AN3 AN4 AN5 AN6
1
Result Register RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3]1 RSLT[0:3]1 RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7]1 RSLT[0:7]1 RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7]
AN71 Reserved Reserved Reserved Reserved VRH VRL (VRH - VRL) / 2 Test/Reserved AN0 AN1 AN2 AN3 AN4 AN5 AN6
1
AN71 Reserved Reserved Reserved Reserved VRH VRL (VRH - VRL) / 2 Test/Reserved
1. AN6 and AN7 are internally connected to VRL. Corresponding result register values always read $0000.
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Table 43 summarizes the operation of S8CM and [CD:CA] when MULT is set (multichannel mode). Number of conversions per channel is determined by SCAN. Channel numbers are given in order of conversion. Table 43 Multiple-Channel Conversions
S8CM 0 CD 0 CC 0 CB X CA X Input AN0 AN1 AN2 AN3 0 0 1 X X AN4 AN5 AN61 AN71 0 1 0 X X Reserved Reserved Reserved Reserved 0 1 1 X X VRH VRL (VRH - VRL) / 2 Test/Reserved 1 0 X X X AN0 AN1 AN2 AN3 AN4 AN5 AN61 AN71 1 1 X X X Reserved Reserved Reserved Reserved VRH VRL (VRH - VRL) / 2 Test/Reserved Result Register RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT21 RSLT31 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT61 RSLT71 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7
1. AN6 and AN7 are internally connected to VRL. Corresponding result register values always read $0000.
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ADSTAT -- ADC Status Register
SCF 0 15 14 13 NOT USED 12 11 10 CCTR[2:0] 0 9 8 7 6 5 4 CCF[7:0] 3 2
$YFF70E
1 0
RESET:
0
0
0
0
0
0
0
0
0
0
ADSTAT contains information related to the status of a conversion sequence. SCF -- Sequence Complete Flag 0 = Sequence not complete 1 = Sequence complete SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first conversion sequence when SCAN is set. SCF is cleared when ADCTL1 is written and a new conversion sequence begins. CCTR[2:0] -- Conversion Counter Field This field reflects the contents of the conversion counter pointer in either four or eight count conversion sequence. The value corresponds to the number of the next result register to be written, and thus indicates which channel is being converted. CCF[7:0] -- Conversion Complete Field Each bit in this field corresponds to an A/D result register (CCF7 to RSLT7, etc.). A bit is set when conversion for the corresponding channel is complete, and remains set until the result register is read. RSLT[0:7] -- A/D Result Registers $YFF710-$YFF73E
The result registers are used to store data after conversion is complete. Each register can be read from three different addresses in the register block. Data format depends on the address from which it is read. RJURR[0:7] -- Unsigned Right-Justified Format $YFF710-$YFF71F
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution. For 8-bit conversions, bits [7:0] contain data and bits [9:8] are zero. Bits [15:10] always return zero when read. LJSRR[0:7] -- Signed Left-Justified Format $YFF720-$YFF72F
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution. For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Although the ADC is unipolar, it is assumed that the zero point is halfway between low and high reference when this format is used -- for positive input, bit 15 = 0, for negative input, bit 15 = 1. Bits [5:0] always return zero when read. LJURR[0:7] -- Unsigned Left-Justified Format $YFF730-$YFF73F
Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution. For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Bits [5:0] always return zero when read.
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6 General-Purpose Timer Module
The GPT is a simple, yet flexible 11-channel timer used in systems where a moderate degree of external visibility and control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. A bus interface unit connects the GPT to the intermodule bus. Figure 14 shows a block diagram of the GPT.
IC1/PGP0 IC2/PGP1 IC3/PGP2
CAPTURE/COMPARE UNIT
OC1/PGP3 OC2/OC1/PGP4 OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PCLK PWMA PWMB
PULSE ACCUMULATOR
PRESCALER
PWM UNIT BUS INTERFACE
IMB
GPT BLOCK
Figure 14 GPT Block Diagram 6.1 Overview The capture/compare unit features three input capture channels, four output compare channels and one selectable input capture/output compare channel. These channels share a 16-bit free-running counter (TCNT), which derives its clock from a nine-stage prescaler or from the external clock input signal (PCLK). Pulse accumulator channel logic includes an 8-bit counter; the pulse accumulator can operate in either event counting mode or gated time accumulation mode. Pulse-width modulator outputs are periodic waveforms whose duty cycles can be independently selected and modified by user software. The PWM circuits share a 16-bit free-running counter that can be clocked by the same nine-stage prescaler used by the capture/compare unit or by the PCLK input. All GPT pins can also be used for general-purpose input/output. The input capture and output compare pins form a bidirectional 8-bit parallel port (PORTGP). PWM pins are outputs only. PAI and PCLK pins are inputs only. GPT input capture/output compare pins are bidirectional and can be used to form an 8-bit parallel port. The pulse-width modulator outputs can be used as general-purpose outputs. The PAI and PCLK inputs can be used as general-purpose inputs.
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6.2 GPT Address Map Table 44 shows the GPT address map.
Table 44 GPT Address Map
Address $YFF9001 $YFF902 $YFF904 $YFF906 $YFF908 $YFF90A $YFF90C $YFF90E $YFF910 $YFF912 $YFF914 $YFF916 $YFF918 $YFF91A $YFF91C $YFF91E $YFF920 $YFF922 $YFF924 $YFF926 $YFF928 $YFF92A $YFF92C $YFF92E- $YFF93F 15 8 7 0 GPT MODULE CONFIGURATION REGISTER (GPTMCR) GPT MODULE TEST REGISTER (GPTMTR) INTERRUPT CONFIGURATION REGISTER (ICR) PGP DATA DIRECTION (DDRGP) OC1 ACTION MASK (OC1M) PULSE ACCUMULATOR CONTROL (PACTL) PGP DATA (PORTGP) OC1 ACTION DATA (OC1D) PULSE ACCUMULATOR COUNTER (PACNT)
TIMER COUNTER (TCNT)
TIMER INPUT CAPTURE 1 (TIC1) TIMER INPUT CAPTURE 2 (TIC2) TIMER INPUT CAPTURE 3 (TIC3) TIMER OUTPUT COMPARE 1 (TOC1) TIMER OUTPUT CAPTURE 2 (TOC2) TIMER OUTPUT CAPTURE 3 (TOC3) TIMER OUTPUT CAPTURE 4 (TOC4) TIMER INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5) TIMER CONTROL 1 (TCTL1) TIMER MASK 1 (TMSK1) TIMER FLAG 1 (TFLG1) FORCE COMPARE (CFORC) PWMA DUTY CYCLE (PWMA) PWMA BUFFER (PWMBUFA) TIMER CONTROL 2 (TCTL2) TIMER MASK 2 (TMSK2) TIMER FLAG 2 (TFLG2) PWM CONTROL C (PWMC) PWMB DUTY CYCLE (PWMB) PWMB BUFFER (PWMBUFB)
PWM COUNT REGISTER (PWMCNT) GPT PRESCALER (PRESCL) RESERVED
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIMCR.
6.3 Capture/Compare Unit The capture/compare unit features three input capture channels, four output compare channels, and one input capture/output compare channel (function selected by control register). Refer to Figure 15. These channels share a 16-bit free-running counter (TCNT), which derives its clock from seven stages of a 9-stage prescaler. Refer to Figure 16. This section also contains one pulse accumulator channel. The pulse accumulator logic includes its own 8-bit counter and can operate in either event counting mode or gated time accumulation mode. Refer to Figure 17.
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PCLK CLOCK
PRESCALER - DIVIDE BY 4, 8, 16, 32, 64, 128, 256 1 OF 8 SELECT CPR2 CPR1 CPR0 16-BIT TIMER BUS
TCNT (HI)
16-BIT FREE RUNNING COUNTER
TCNT (LO)
TOI TOF
9
INTERRUPT REQUESTS
IC1I TIC1 (HI) TIC2 (HI) TIC3 (HI) 16-BIT LATCH CLK TIC1 (LO) TIC2 (LO) TIC3 (LO) 16-BIT LATCH CLK 16-BIT LATCH CLK IC1F IC2F IC3F OC1I OC1F FOC1 OC2F FOC2 OC3F FOC3 OC4F FOC4 OC5 IC4 I4/O5 I4/O5F FOC5 I4/O5I OC4I OC3I OC2I IC2I IC3I
1 2 3
PIN FUNCTIONS BIT 0 BIT 1 BIT 2 PGP0 IC1 PGP1 IC2 PGP2 IC3
16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO)
4 BIT 3 5 BIT 4 6 BIT 5 7 BIT 6 8 BIT 7 PGP6 OC4/OC1 PGP7 IC4/OC5/ OC1 PGP5 OC3/OC1 PGP3 OC1 PGP4 OC2/OC1
16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO)
16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO)
16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO)
TI4/O5 (HI) TI4/O5 (LO)
16-BIT COMPARATOR = 16-BIT LATCH CLK
TFLG1 STATUS FLAGS
CFORC FORCE OUTPUT COMPARE
TMSK1 INTERRUPT ENABLES
PARALLEL PORT PIN CONTROL
16/32 CC BLOCK
Figure 15 GPT Capture/Compare Block Diagram
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SYSTEM CLOCK
DIVIDER /128 /256 /512 /16 /32 /64 /2 /4 /8
/512 EXT.
TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR
CPR2 CPR1 CPR0 /256 /128 /64 /32 /16 /8 /4 EXT.
SELECT
TO CAPTURE/ COMPARE TIMER
/128 /64 /32 /16 /8 /4 /2 EXT. PCLK PIN SYNCHRONIZER AND DIGITAL FILTER
SELECT
TO PWM UNIT
PPR2 PPR1 PPR0
GPT PRE BLOCK
Figure 16 Prescaler Block Diagram
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10 INTERRUPT REQUESTS 11
TMSK2
PAOVF EDGE DETECT LOGIC 2:1 MUX
PAOVI
PAI
SYNCHRONIZER & DIGITAL FILTER
OVERFLOW
PAIF TFLG2 PACNT 8-BIT COUNTER
PAII
ENABLE
PAMOD
PEDGE PACTL PACLK1 PACLK0 PCLKS
PAEN
PAIS
PCLK
TCNT OVERFLOW CAPTURE/COMPARE CLK PRESCALER / 512
INTERNAL DATA BUS
MUX
16/32 PULSE ACC BLOCK
Figure 17 Pulse Accumulator Block Diagram 6.4 Pulse-Width Modulator The pulse-width modulation submodule has two output pins. The outputs are periodic waveforms controlled by a single frequency whose duty cycles can be independently selected and modified by user software. Each PWM can be independently programmed to run in fast or slow mode. The PWM unit has its own 16-bit free-running counter, which is clocked by an output of the nine-stage prescaler (the same prescaler used by the capture/compare unit) or by the clock input pin, PCLK. Figure 18 displays a block diagram of the PWM unit.
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16-BIT DATA BUS
PWMA REGISTER
PWMB REGISTER
PWMABUF REGISTER
PWMBBUF REGISTER
"A" COMPARATOR PWMA PIN F1A BIT R LATCH S 8-BIT ZERO DETECTOR
"B" COMPARATOR R LATCH S 8-BIT ZERO DETECTOR
PWMB PIN F1B BIT
SFA BIT
"A" MULTIPLEXER
"B" MULTIPLEXER
SFB BIT
16-BIT COUNTER
[14:0]
FROM PRESCALER CLOCK
16/32 PWM BLOCK
Figure 18 PWM Unit Block Diagram
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6.5 GPT Registers The following section provides a summary of GPT registers and their contents. GPTMCR -- GPT Module Configuration Register
STOP 0 15 FRZ1 0 14 FRZ0 0 13 STOPP 0 12 INCP 0 11 10 0 0 9 0 0 8 0 0 SUPV 1 7 6 0 0 5 0 0 4 0 0 3 2
$YFF900
IARB[3:0] 0 0 1 0
RESET:
0
0
The GPTMCR contains parameters for configuring the GPT. STOP -- Stop Clocks 0 = Internal clocks not shut down 1 = Internal clocks shut down FRZ1 -- Not Implemented FRZ0 -- FREEZE Assertion Response 0 = Ignore IMB FREEZE Signal 1 = FREEZE the current state of the GPT STOPP -- Stop Prescaler 0 = Normal operation 1 = Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins. INCP -- Increment Prescaler 0 = Has no meaning 1 = If STOPP is asserted, increment prescaler once and clock input synchronizers once. SUPV -- Supervisor/Unrestricted Data Space This bit has no effect because the CPU16 always operates in the supervisor mode. IARB[3:0] -- Interrupt Arbitration Identification The value in this field is used to arbitrate between simultaneous interrupt service requests of the same priority. Each module that can generate interrupts has an IARB field. In order to implement an arbitration scheme, each IARB field must be set to a different non-zero value. If an interrupt request from a module that has an IARB field value of $0 is recognized, the CPU16 processes a spurious interrupt exception. The reset value of all IARB fields other than that of the SCIM is $0 (no priority), to preclude interrupt processing during reset. GPTMTR -- GPT Module Test Register This address is reserved for GPT factory test. ICR -- GPT Interrupt Configuration Register
15 14 IPA[3:0] 13 12 11 0 0 10 IPL[2:0] 0 9 8 7 6 IVBA[3:0] 5 4 3 0 0 2 0 0
$YFF902
$YFF904
1 0 0 0 0 0
0
RESET:
0
0
0
0
0
0
0
0
0
IPA[3:0] -- Interrupt Priority Adjust This field specifies which GPT interrupt source is given highest internal priority. Refer to Table 45.
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MOTOROLA 93
Table 45 GPT Interrupt Sources
Name -- IC1 IC2 IC3 OC1 OC2 OC3 OC4 IC4/OC5 TO PAOV PAI Source Number 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Source Adjusted Channel Input Capture 1 Input Capture 2 Input Capture 3 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Input Capture 4/Output Compare 5 Timer Overflow Pulse Accumulator Overflow Pulse Accumulator Input Vector Number IVBA : 0000 IVBA : 0001 IVBA : 0010 IVBA : 0011 IVBA : 0100 IVBA : 0101 IVBA : 0110 IVBA : 0111 IVBA : 1000 IVBA : 1001 IVBA : 1010 IVBA : 1011
IPL[2:0] -- Interrupt Priority Level This field specifies the priority level of interrupts generated by the GPT. IVBA[3:0] -- Interrupt Vector Base Address Most significant nibble of interrupt vector numbers generated by the GPT. Refer to Table 45. DDRGP/PORTGP -- Port GP Data Direction Register/Port GP Data Register
15 14 13 12 DDRGP 11 10 9 8 7 6 5 4 PORTGP 3 2
$YFF906
1 0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and PORTGP holds the 8-bit data. DDRGP[7:0] -- Port GP Data Direction Register 0 = Input only 1 = Output OC1M/OC1D -- OC1 Action Mask Register/OC1 Action Data Register
15 14 OC1M[5:1] 0 13 12 11 10 0 0 9 0 0 8 0 0 7 6 OC1D[5:1] 0 5 4 3 2 0 0
$YFF908
1 0 0 0 0 0
0
RESET:
0
0
0
0
0
0
0
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which pins are affected. OC1D determines what the outputs are. OC1M[5:1] -- OC1 Mask Field 0 = Corresponding output compare pin is not affected by OC1 compare. 1 = Corresponding output compare pin is affected by OC1 compare. OC1M[5:1] correspond to OC[5:1]. OC1D[5:1] -- OC1 Data Field 0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match. 1 = If OC1 mask bit is set, set the corresponding output compare pin on OC1 match. OC1D[5:1] correspond to OC[5:1].
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MC68HC916X1 MC68HC916X1TS/D
TCNT -- Timer Counter Register
$YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the GPT module. PACTL/PACNT -- Pulse Accumulator Control Register/Counter
PAIS U 15 PAEN 0 14 PAMOD PEDGE PCLKS 0 0 0 13 12 11 I4/O5 0 10 PACLK[1:0] 0 0 9 8 7 6 PULSE ACCUMULATOR COUNTER 0 0 0 0 5 4 3 2
$YFF90C
1 0
RESET:
0
0
0
0
PACTL enables the pulse accumulator and selects either event counting or gated mode. In event counting mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an internal clock. PAIS -- PAI Pin State (Read Only) PAEN -- Pulse Accumulator Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD -- Pulse Accumulator Mode 0 = External event counting 1 = Gated time accumulation PEDGE -- Pulse Accumulator Edge Control The effects of PAMOD and PEDGE are shown in Table 46. Table 46 PAMOD/PEDGE Effects
PAMOD 0 0 1 1 PEDGE 0 1 0 1 Effect PAI falling edge increments counter PAI rising edge increments counter Zero on PAI inhibits counting One on PAI inhibits counting
PCLKS -- PCLK Pin State (Read Only) I4/O5 -- Input Capture 4/Output Compare 5 0 = Output compare 5 enabled 1 = Input capture 4 enabled PACLK[1:0] -- Pulse Accumulator Clock Select (Gated Mode) Table 47 shows the PACLK[1:0] bit field effects. Table 47 PACLK[1:0] Bit Field
PACLK[1:0] 00 01 10 11 Pulse Accumulator Clock Selected System clock divided by 512 Same clock used to increment TCNT TOF flag from TCNT External clock, PCLK
PACNT -- Pulse Accumulator Counter Eight-bit read/write counter used for external event counting or gated time accumulation.
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TIC[1:3] -- Input Capture Registers 1-3 $YFF90E, $YFF910, $YFF912 The input capture registers are 16-bit read-only registers which are used to latch the value of TCNT when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF. TOC[1:4] -- Output Compare Registers 1-4 $YFF914, $YFF916, $YFF918, $YFF91A The output compare registers are 16-bit read/write registers which can be used as output waveform controls or as elapsed time indicators. For output compare functions, they are written to a desired match value and compared against TCNT to control specified pin actions. They are reset to $FFFF. TI4/O5 -- Input Capture 4/Output Compare 5 Register $YFF91C This register serves either as input capture register 4 or output compare register 5, depending on the state of I4/O5 in PACTL. TCTL1/TCTL2 -- Timer Control Registers 1-2
OM5 0 15 OL5 0 14 OM4 0 13 OL4 0 12 OM3 0 11 OL3 0 10 OM2 0 9 OL2 0 8 7 6 5 4 3 2
$YFF91E
EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A 0 0 0 0 0 0 0 0 1 0
RESET:
TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input capture to be performed. OM/OL[5:2] -- Output Compare Mode Bits and Output Compare Level Bits Each pair of bits specifies an action to be taken when output comparison is successful. Refer to Table 48. Table 48 OM/OL[5:2] Bit Field Effects
OM/OL[5:2] 00 01 10 11 Action Taken Timer disconnected from output logic Toggle OCx output line Clear OCx output line to 0 Set OCx output line to 1
EDG[4:1]B/A -- Input Capture Edge Control Bits Each pair of bits configures input sensing logic for the corresponding input capture. Refer to Table 49. Table 49 EDG[4:1]B/A Bit Field Effects
EDG[4:1]B/A 00 01 10 11 Configuration Capture disabled Capture on rising edge only Capture on falling edge only Capture on any (rising or falling) edge
TMSK1/TMSK2 -- Timer Interrupt Mask Registers 1-2
I4/O5I 0 15 14 13 OCI[4:1] 12 11 10 ICI[3:1] 0 9 8 TOI 0 7 6 0 0 PAOVI 0 5 PAII 0 4 CPROUT 0 3 2
$YFF920
CPR[2:0] 0 1 0
RESET:
0
0
0
0
0
0
0
0
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MC68HC916X1 MC68HC916X1TS/D
TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT functions. I4/O5I -- Input Capture 4/Output Compare 5 Interrupt Enable 0 = IC4/OC5 interrupt disabled. 1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set. OCI[4:1] -- Output Compare Interrupt Enable 0 = OC interrupt disabled 1 = OC interrupt requested when OC flag set OCI[4:1] correspond to OC[4:1]. ICI[3:1] -- Input Capture Interrupt Enable 0 = IC interrupt disabled 1 = IC interrupt requested when IC flag set ICI[3:1] correspond to IC[3:1]. TOI -- Timer Overflow Interrupt Enable 0 = Timer overflow interrupt disabled 1 = Interrupt requested when TOF flag is set PAOVI -- Pulse Accumulator Overflow Interrupt Enable 0 = Pulse accumulator overflow interrupt disabled 1 = Interrupt requested when PAOVF flag is set PAII -- Pulse Accumulator Input Interrupt Enable 0 = Pulse accumulator interrupt disabled 1 = Interrupt requested when PAIF flag is set CPROUT -- Compare/Capture Unit Clock Output Enable 0 = Normal operation for OC1 pin 1 = TCNT clock driven out OC1 pin CPR[2:0] -- Timer Prescaler/PCLK Select Field This field selects one of seven prescaler taps or PCLK to be TCNT input. Refer to Table 50. Table 50 CPR[2:0] Bit Field Effects
CPR[2:0] 000 001 010 011 100 101 110 111 System Clock Divide-By Factor 4 8 16 32 64 128 256 PCLK
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TFLG1/TFLG2 -- Timer Interrupt Flag Registers 1-2
I4/O5F 0 15 14 13 OCF[4:1] 12 11 10 ICF[3:1] 0 9 8 TOF 0 7 6 0 0 PAOVF 0 5 PAIF 0 4 3 0 0 2 0 0
$YFF922
1 0 0 0 0 0
RESET:
0
0
0
0
0
0
These registers show condition flags that correspond to various GPT events. If the corresponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs. I4/O5F -- Input Capture 4/Output Compare 5 Flag When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the value in TOC5. When I4/O5 in PACTL is one, the flag is set each time a selected edge is detected at the I4/O5 pin. OCF[4:1] -- Output Compare Flags An output compare flag is set each time TCNT matches the corresponding TOC register. OCF[4:1] correspond to OC[4:1]. ICF[3:1] -- Input Capture Flags A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] correspond to IC[3:1]. TOF -- Timer Overflow Flag This flag is set each time TCNT advances from a value of $FFFF to $0000. PAOVF -- Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of $FF to $00. PAIF -- Pulse Accumulator Flag In event counting mode, this flag is set when an active edge is detected on the PAI pin. In gated time accumulation mode, PAIF is set at the end of the timed period. CFORC/PWMC -- Compare Force Register/PWM Control Register
15 14 FOC[5:1] 0 13 12 11 10 0 0 FPWMA FPWMB PPROUT 0 0 0 9 8 7 6 PPR[2:0] 0 5 4 SFA 0 3 SFB 0 2
$YFF924
F1A 0 1 F1B 0 0
0
RESET:
0
0
0
0
0
Setting a bit in CFORC causes a specific output on OC. PWMC controls operation of the GPT PWM submodule. FOC[5:1] -- Force Output Compare 0 = Causes no action on corresponding OC pin. 1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set. FOC[5:1] correspond to OC[5:1]. FPWMA/B -- Force PWM Value 0 = PWM pin A/B is used for PWM functions; normal operation. 1 = PWM pin A/B is used for discrete output. The value of the F1A/B bit will be driven out on the PWMA/B pin. This is true for PWMA regardless of the state of the PPROUT bit. PPROUT -- PWM Clock Output Enable 0 = Normal PWM operation on PWMA 1 = Clock selected by PPR[2:0] is driven out PWMA pin.
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MC68HC916X1 MC68HC916X1TS/D
PPR[2:0] -- PWM Prescaler/PCLK Select This field selects one of seven prescaler taps, or PCLK, to be PWMCNT input. Refer to Table 51. Table 51 PWM Prescaler/PCLK Select Taps
PPR[2:0] 000 001 010 011 100 101 110 111 System Clock Divide-By Factor 2 4 8 16 32 64 128 PCLK
SFA/B -- PWMA/B Slow/Fast Select 0 = PWMA/B period is 256 PWMCNT increments long. 1 = PWMA/B period is 32768 PWMCNT increments long. Table 52 shows the effects of settings on PWM frequency for a 16.78-MHz system clock. Table 52 Effects of SFA/B Settings on PWM Frequency
PPR[2:0] 000 001 010 011 100 101 110 111 Prescaler Tap Div 2 = 8.39 MHz Div 4 = 4.19 MHz Div 8 = 2.10 MHz Div 16 = 1.05 MHz Div 32 = 524 kHz Div 64 = 262 kHz Div 128 = 131 kHz PCLK SFA/B = 0 32.8 kHz 16.4 kHz 8.19 kHz 4.09 kHz 2.05 kHz 1.02 kHz 512 Hz PCLK/256 SFA/B = 1 256 Hz 128 Hz 64.0 Hz 32.0 Hz 16.0 Hz 8.0 Hz 4.0 Hz PCLK/32768
F1A/B -- Force Logic Level One on PWMA/B 0 = Force logic level zero output on PWMA/B pin 1 = Force logic level one output on PWMA/B pin PWMA/PWMB -- PWM Duty Cycle Registers A/B $YFF926, $YFF927
These registers are associated with the pulse-width value of the PWM output on the corresponding PWM pin. A value of $00 loaded into one of these registers results in a continuously low output on the corresponding pin. A value of $80 results in a 50% duty cycle output. Maximum value ($FF) selects an output that is high for 255/256 of the period. PWMCNT -- PWM Count Register $YFF928
PWMCNT is the 16-bit free-running counter associated with the PWM functions of the GPT module. PWMBUFA/B -- PWM Buffer Registers A/B $YFF92A, $YFF92B
These read-only registers contain values associated with the duty cycles of the corresponding PWM. Reset state for both registers is $00. PRESCL -- GPT Prescaler $YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000.
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MOTOROLA 99
7 Queued Serial Module
The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). Figure 19 shows the QSM block diagram.
QSPI
MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6
INTERFACE LOGIC
PORT QS
IMB
TXD/PQS7 SCI RXD
QSM BLOCK
Figure 19 QSM Block Diagram 7.1 Overview The QSPI provides peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral chip-select pins provide addressability for up to 16 peripheral devices. A self-contained RAM queue allows up to 16 serial transfers of 8 to 16 bits each, or transmission of a 256-bit data stream without CPU intervention. A special wraparound mode supports continuous sampling of a serial peripheral, with automatic QSPI RAM updating, which makes the interface to A/D converters more efficient. The SCI provides a standard nonreturn to zero (NRZ) mark/space format. It operates in either fullor half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78 MHz system clock. Word length of either 8 or 9 bits is software selectable. Optional parity generation and detection provide either even or odd parity check capability. Advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. Wake-up functions allow the CPU to run uninterrupted until meaningful data is available. Table 53 shows the address map of the QSM.
MOTOROLA 100
MC68HC916X1 MC68HC916X1TS/D
Table 53 QSM Address Map
Address $YFFC00
1
15
8
7
0
QSM MODULE CONFIGURATION (QSMCR) QSM TEST (QTEST) QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR) RESERVED SCI CONTROL 0 REGISTER (SCCR0) SCI CONTROL 1 REGISTER (SCCR1) SCI STATUS REGISTER (SCSR) SCI DATA REGISTER (SCDR) RESERVED RESERVED NOT USED PQS DATA (PORTQS) PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS) SPI CONTROL 0 REGISTER (SPCR0) SPI CONTROL 1 REGISTER (SPCR1) SPI CONTROL 2 REGISTER (SPCR2) SPI CONTROL 3 REGISTER (SPCR3) SPI STATUS REGISTER (SPSR)
$YFFC02 $YFFC04 $YFFC06 $YFFC08 $YFFC0A $YFFC0C $YFFC0E $YFFC10 $YFFC12 $YFFC14 $YFFC16 $YFFC18 $YFFC1A $YFFC1C $YFFC1E $YFFC20- $YFFCFF $YFFD00- $YFFD1F $YFFD20- $YFFD3F $YFFD40- $YFFD4F
RESERVED RECEIVE RAM (RR[0:F]) TRANSMIT RAM (TR[0:F]) COMMAND RAM (CR[0:F])
1. Y = M111, where M is the logic state of the MM bit in the SCIMCR.
7.2 Pin Function Table 54 is a summary of the functions of the QSM pins when they are not configured for generalpurpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an input or output. Table 54 QSM Pin Functions
Pin MISO MOSI SCK PCS0/SS Mode Master Slave Master Slave Master Slave Master Slave PCS[3:1] TXD RXD Master Slave Transmit Receive Pin Function Serial Data Input to QSPI Serial Data Output from QSPI Serial Data Output from QSPI Serial Data Input to QSPI Clock Output from QSPI Clock Input to QSPI Input: Assertion Causes Mode Fault Output: Selects Peripherals Input: Selects the QSPI Output: Selects Peripherals None Serial Data Output from SCI Serial Data Input to SCI
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7.3 QSM Registers QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unimplemented bits always return a logic zero value. 7.3.1 Global Registers The QSM global registers contain system parameters used by both the QSPI and the SCI submodules. These registers contain the bits and fields used to configure the QSM. QSMCR -- QSM Configuration Register
STOP 0 15 FRZ1 0 14 FRZ0 0 13 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 SUPV 0 7 6 0 0 5 0 0 4 0 0 3 2
$YFFC00
IARB[3:0] 1 0
RESET:
0
0
0
0
The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface. STOP -- Stop Enable 0 = Normal QSM clock operation 1 = QSM clock operation stopped STOP places the QSM in a low-power state by disabling the system clock in most parts of the module. The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is asserted. STOP can be negated by the CPU and by reset. The system software must stop each submodule before asserting STOP to avoid complications at restart and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and the operation should be verified for completion before asserting STOP. The QSPI submodule should be stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set. FRZ1 -- FREEZE Assertion Response 0 = Ignore the FREEZE signal on the IMB 1 = Halt the QSPI (on a transfer boundary) FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted. FREEZE is asserted whenever the CPU enters the background mode. FRZ0 -- Not Implemented Bits [12:8] -- Not Implemented SUPV -- Supervisor/Unrestricted Data Space This bit has no effect because the CPU16 always operates in the supervisor mode. IARB[3:0] -- Interrupt Arbitration Identification Number The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. QTEST -- QSM Test Register QTEST is used during factory testing of the QSM. $YFFC02
MOTOROLA 102
MC68HC916X1 MC68HC916X1TS/D
QILR -- QSM Interrupt Levels Register
15 0 0 14 0 0 13 ILQSPI[2:0] 0 12 11 10 ILSCI[2:0] 0 9 8 7 6 5 4 QIVR 3 2
$YFFC04
1 0
RESET:
0
0
0
0
QILR determines the priority level of interrupts requested by the QSM. ILQSPI[2:0] -- Interrupt Level for QSPI ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (interrupts disabled) to $7 (highest priority). ILSCI[2:0] -- Interrupt Level of SCI ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts disabled) to $7 (highest priority). If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request interrupt service, QSPI has priority. QIVR -- QSM Interrupt Vector Register
15 14 13 12 QILR 11 10 9 8 7 6 5 4 INTV[7:0] 3 2
$YFFC05
1 0
RESET:
0
0
0
0
1
1
1
1
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the exception table. This vector is selected until QIVR is written. A user-defined vector ($40-$FF) should be written to QIVR during QSM initialization. After initialization, QIVR determines which two vectors in the exception vector table are to be used for QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to each other. Both submodules use the same interrupt vector with the least significant bit (LSB) determined by the submodule causing the interrupt. The value of INTV0 used during an interrupt-acknowledge cycle is supplied by the QSM. During an interrupt-acknowledge cycle, INTV[7:1] are driven on DATA[7:1] IMB lines. DATA0 is negated for an SCI interrupt and asserted for a QSPI interrupt. Writes to INTV0 have no meaning or effect. Reads of INTV0 return a value of one. 7.3.2 Pin Control Registers The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose I/ O on a pin-by-pin basis. Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid driving incorrect data, the first byte to be output must be written before DDRQS is configured. DDRQS must then be written to determine the direction of data flow and to output the value contained in register PORTQS. Subsequent data for output is written to PORTQS.
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MOTOROLA 103
PORTQS -- Port QS Data Register
15 14 13 12 NOT USED 11 10 9 8 PQS7 0 7 PQS6 0 6 PQS5 0 5 PQS4 0 4 PQS3 0 3 PQS2 0 2
$YFFC14
PQS1 0 1 PQS0 0 0
RESET:
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS. PQSPAR -- PORT QS Pin Assignment Register DDRQS -- PORT QS Data Direction Register
15 0 0 PQSPA6 PQSPA5 PQSPA4 PQSPA3 0 0 0 0 14 13 12 11 10 0 0 9 8 7 6 5 4 3 2
$YFFC16 $YFFC17
1 0
RESET:
PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0 0 0 0 0 0 0 0 0 0 0
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI. Table 55 displays PQSPAR pin assignments. Table 55 PQSPAR Pin Assignments
PQSPAR Field PQSPA0 PQSPA1 -- PQSPA3 PQSPA4 PQSPA5 PQSPA6 -- PQSPAR Bit 0 1 0 1 -- -- 0 1 0 1 0 1 0 1 -- -- Pin Function PQS0 MISO PQS1 MOSI PQS21 SCK PQS3 PCS0/SS PQS4 PCS1 PQS5 PCS2 PQS6 PCS3 PQS72 TXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it becomes SCI serial output TXD.
DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. Table 56 shows the effect of DDRQS on QSM pin functions.
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Table 56 Effect of DDRQS on QSM Pin Function
QSM Pin MISO Mode Master Slave MOSI Master Slave SCK1 Master Slave PCS0/SS Master Slave PCS[3:1] Master Slave TXD2 RXD Transmit Receive DDQS7 None DDQS[4:6] DDQS3 DDQS2 DDQS1 DDRQS Bit DDQS0 Bit State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X NA Pin Function Serial Data Input to QSPI Disables Data Input Disables Data Output Serial Data Output from QSPI Disables Data Output Serial Data Output from QSPI Serial Data Input to QSPI Disables Data Input Disables Clock Output Clock Output from QSPI Clock Input to QSPI Disables Clock Input Assertion Causes Mode Fault Chip-Select Output QSPI Slave Select Input Disables Select Input Disables Chip-Select Output Chip-Select Output Inactive Inactive Serial Data Output from SCI Serial Data Input to SCI
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it becomes SCI serial output TXD.
DDRQS determines the direction of the TXD pin only when the SCI transmitter is disabled. When the SCI transmitter is enabled, the TXD pin is an output. 7.4 QSPI Submodule The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products. Figure 20 shows a block diagram of the QSPI.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 105
QUEUE CONTROL BLOCK QUEUE POINTER 4 A D D R E S S R E G I S T E R
COMPARATOR
DONE 4
END QUEUE POINTER
80-BYTE QSPI RAM
CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS DELAY COUNTER
4 4
CHIP SELECT COMMAND
MSB
PROGRAMMABLE LOGIC ARRAY
8/16-BIT SHIFT REGISTER Rx/Tx DATA REGISTER
LSB
M S M S
MOSI
MISO PCS0/SS PCS[2:1]
2 BAUD RATE GENERATOR
SCK
QSPI BLOCK
Figure 20 QSPI Block Diagram 7.4.1 QSPI Pins Seven pins are associated with the QSPI. When not needed for a QSPI function, they can be configured as general-purpose I/O pins. The PCS0/SS pin can function as a peripheral chip select output, slave select input, or general-purpose I/O. Refer to Table 57 for QSPI input and output pins and their functions.
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Table 57 QSPI Pins
Pin Name(s) Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select Slave Select Mnemonic(s) MISO MOSI SCK PCS[3:1] PCS0 SS Mode Master Slave Master Slave Master Slave Master Master Master Slave Function Serial Data Input to QSPI Serial Data Output from QSPI Serial Data Output from QSPI Serial Data Input to QSPI Clock Output from QSPI Clock Input to QSPI Select Peripherals Selects Peripheral Causes mode fault Initiates Serial Transfer
7.4.2 QSPI Registers The programmer's model for the QSPI submodule consists of the QSM global and pin control registers, four QSPI control registers, one status register, and the 80-byte QSPI RAM. The CPU can read and write to registers and RAM. The four control registers must be initialized before the QSPI is enabled to ensure defined operation. SPCR1 should be written last because it contains QSPI enable bit SPE. Asserting this bit starts the QSPI. The QSPI control registers are reset to a defined state and can then be changed by the CPU. Reset values are shown below each register. Table 58 shows a memory map of the QSPI. Table 58 QSPI Memory Map
Address $YFFC18 $YFFC1A $YFFC1C $YFFC1E $YFFC1F $YFFD00 $YFFD20 $YFFD40 Name SPCR0 SPCR1 SPCR2 SPCR3 SPSR RR[0:F] TR[0:F] CR[0:F] Usage QSPI Control Register 0 QSPI Control Register 1 QSPI Control Register 2 QSPI Control Register 3 QSPI Status Register QSPI Receive Data (16 Words) QSPI Transmit Data (16 Words) QSPI Command Control (8 Words)
Writing a different value into any control register except SPCR2 while the QSPI is enabled disrupts operation. SPCR2 is buffered to prevent disruption of the current serial transfer. After completion of the current serial transfer, the new SPCR2 values become effective. Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect on QSPI operation. Rewriting NEWQP[3:0] in SPCR2 causes execution to restart at the designated location.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 107
SPCR0 -- QSPI Control Register 0
MSTR 0 15 WOMQ 0 14 13 12 BITS[3:0] 11 10 CPOL 0 9 CPHA 1 8 7 6 5 4 SPBR[7:0] 3 2
$YFFC18
1 0
RESET:
0
0
0
0
0
0
0
0
0
1
0
0
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write this register. The QSM has read-only access. MSTR -- Master/Slave Mode Select 0 = QSPI is a slave device and only responds to externally generated serial data. 1 = QSPI is system master and can initiate transmission to external SPI devices. MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and may only be written by the CPU. WOMQ -- Wired-OR Mode for QSPI Pins 0 = Outputs have normal MOS drivers. 1 = Pins designated for output by DDRQS have open-drain drivers. WOMQ allows the wired-OR function to be used on QSPI pins, regardless of whether they are used as general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins regardless of whether the QSPI is enabled or disabled. BITS[3:0] -- Bits Per Transfer In master mode, when BITSE in a command is set, the BITS[3:0] field determines the number of data bits transferred. When BITSE is cleared, eight bits are transferred. Reserved values default to eight bits. In slave mode, the command RAM is not used and the setting of BITSE has no effect on QSP1 transfers. Instead, the BITS[3:0] field determines the number of bits the QSPI will receive during each transfer before storing the received data. Table 59 shows the number of bits per transfer. Table 59 Bits Per Transfer
BITS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits per Transfer 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8 9 10 11 12 13 14 15
MOTOROLA 108
MC68HC916X1 MC68HC916X1TS/D
CPOL -- Clock Polarity 0 = The inactive state value of SCK is logic level zero. 1 = The inactive state value of SCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce a desired clock/data relationship between master and slave devices. CPHA -- Clock Phase 0 = Data is captured on the leading edge of SCK and changed on the following edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK. CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices. CPHA is set at reset. SPBR[7:0] -- Serial Clock Baud Rate The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is selected by writing a value from 2 to 255 into the SPBR[7:0] field. The following equation determines the SCK baud rate: System Clock SCK Baud Rate = -----------------------------------2 x SPBR[7:0] or System Clock SPBR[7:0] = ------------------------------------------------------------------------2 x SCK Baud Rate Desired Giving SPBR[7:0] a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the system clock frequency. SPRC1 -- QSPI Control Register 1
SPE 0 15 14 13 12 DSCKL[6:0] 0 11 10 9 8 7 6 5 4 DTL[7:0] 3 2
$YFFC1A
1 0
RESET:
0
0
0
1
0
0
0
0
0
0
0
1
0
0
SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write this register, but the QSM has read access only, except for SPE, which is automatically cleared by the QSPI after completing all serial transfers, or when a mode fault occurs. SPE -- QSPI Enable 0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O. 1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI. DSCKL[6:0] -- Delay before SCK When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation determines the actual delay before SCK: DSCKL[6:0] PCS to SCK Delay = ----------------------------------System Clock where DSCKL[6:0] equals {1, 2, 3,..., 127}. When the DSCK value of a queue entry equals zero, then DSCKL[6:0] is not used. Instead, the PCS valid-to-SCK transition is one-half SCK period.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 109
DTL[7:0] -- Length of Delay after Transfer When the DT bit in command RAM is set, this field determines the length of delay after serial transfer. The following equation is used to calculate the delay: 32 x DTL[7:0] Delay after Transfer = ----------------------------------System Clock where DTL equals {1, 2, 3,..., 255}. A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/System Clock. If DT equals zero, a standard delay is inserted. 17 Standard Delay after Transfer = ----------------------------------System Clock Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. SPCR2 -- QSPI Control Register 2
SPIFIE 0 15 WREN 0 14 WRTO 0 13 12 0 0 11 10 ENDQP[3:0] 0 0 9 8 7 0 0 6 0 0 5 0 0 4 0 0 3 2
$YFFC1C
NEWQP[3:0] 0 0 1 0
RESET:
0
0
0
0
SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value while the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the next serial transfer. Reads of SPCR2 return the current value of the register, not of the buffer. SPIFIE -- SPI Finished Interrupt Enable 0 = QSPI interrupts disabled 1 = QSPI interrupts enabled SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SPIF. WREN -- Wrap Enable 0 = Wraparound mode disabled 1 = Wraparound mode enabled WREN enables or disables wraparound mode. WRTO -- Wrap To When wraparound mode is enabled, after the end of queue has been reached, WRTO determines which address the QSPI executes. Bit 12 -- Not Implemented ENDQP[3:0] -- Ending Queue Pointer This field contains the last QSPI queue address. Bits [7:4] -- Not Implemented NEWQP[3:0] -- New Queue Pointer Value This field contains the first QSPI queue address.
MOTOROLA 110
MC68HC916X1 MC68HC916X1TS/D
SPCR3 -- QSPI Control Register
15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 LOOPQ 0 10 HMIE 0 9 HALT 0 8 7 6 5 4 SPSR 3 2
$YFFC1E
1 0
RESET:
SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM has read-only access. Bits [15:11] -- Not Implemented LOOPQ -- QSPI Loop Mode 0 = Feedback path disabled 1 = Feedback path enabled LOOPQ controls feedback on the data serializer for testing. HMIE -- HALTA and MODF Interrupt Enable 0 = HALTA and MODF interrupts disabled 1 = HALTA and MODF interrupts enabled HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR. HALT -- Halt 0 = Halt not enabled 1 = Halt enabled When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can later be restarted. SPSR -- QSPI Status Register
15 14 13 12 SPCR3 11 10 9 8 SPIF 0 7 MODF 0 6 HALTA 0 5 4 0 0 3 2
$YFFC1F
CPTQP[3:0] 0 0 1 0
RESET:
0
0
SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU reads this register to obtain status information and writes it to clear status flags. SPIF -- QSPI Finished Flag 0 = QSPI not finished 1 = QSPI finished SPIF is set after execution of the command at the address in ENDQP[3:0]. MODF -- Mode Fault Flag 0 = Normal operation 1 = Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode (SS input taken low). The QSPI asserts MODF when the QSPI is the serial master (MSTR = 1) and the SS input pin is negated by an external driver. HALTA -- Halt Acknowledge Flag 0 = QSPI not halted 1 = QSPI halted HALTA is asserted when the QSPI halts in response to CPU assertion of HALT. Bit 4 -- Not Implemented
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 111
CPTQP[3:0] -- Completed Queue Pointer CPTQP[3:0] points to the last command executed. It is updated when the current command is complete. When the first command in a queue is executing, CPTQP[3:0] contains either the reset value ($0) or a pointer to the last command completed in the previous queue. 7.4.3 QSPI RAM The QSPI contains an 80-byte block of dual-access static RAM that is used by both the QSPI and the CPU. The RAM is divided into three segments: receive data, transmit data, and command control data. Receive data is information received from a serial device external to the MCU. Transmit data is information stored by the CPU for transmission to an external peripheral. Command control data is used to perform the transfer. Figure 21 displays the organization of the RAM.
500 RR0 RR1 RR2 RECEIVE RAM RRD RRE RRF WORD 520 TR0 TR1 TR2 TRANSMIT RAM TRD TRE TRF WORD 540 CR0 CR1 CR2 COMMAND RAM CRD CRE CRF BYTE
51E
53E
54F
QSPI RAM MAP
Figure 21 QSPI RAM Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the CPU or waits for CPU intervention. It is possible to execute a queue of commands repeatedly without CPU intervention. RR[0:F] -- Receive Data RAM $YFFD00
Data received by the QSPI is stored in this segment. The CPU reads this segment to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, word, or long-word addressing. The CPTQP[3:0] value in SPSR shows which queue entries have been executed. The CPU uses this information to determine which locations in receive RAM contain valid data before reading them. TR[0:F] -- Transmit Data RAM $YFFD20
Data that is to be transmitted by the QSPI is stored in this segment. The CPU usually writes one word of data into this segment for each queue command to be executed. Information to be transmitted must be written to transmit data RAM in a right-justified format. The QSPI cannot modify information in the transmit data RAM. The QSPI copies the information to its data serializer for transmission. Information remains in transmit RAM until overwritten.
MOTOROLA 112
MC68HC916X1 MC68HC916X1TS/D
CR[0:F] -- Command RAM
$YFFD40
7 CONT
6 BITSE
5 DT
4 DSCK
3 PCS3
2 PCS2
1 PCS1
0 PCS01
-
-
-
-
-
-
-
-
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS01
COMMAND CONTROL 1. The PCS0 bit represents the dual-function PCS0/SS.
PERIPHERAL CHIP SELECT
Command RAM is used by the QSPI when in master mode. The CPU writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the address in NEWQP[3:0] through the address in ENDQP[3:0]. (Both of these fields are in SPCR2). CONT -- Continue 0 = Control of chip selects returned to PORTQS after transfer is complete. 1 = Peripheral chip selects remain asserted after transfer is complete. BITSE -- Bits per Transfer Enable 0 = 8 bits 1 = Number of bits set in BITS[3:0] field of SPCR0 DT -- Delay after Transfer The QSPI provides a variable delay at the end of serial transfer to facilitate the interface with peripherals that have a latency requirement. The delay between transfers is determined by the SPCR1 DTL[6:0] field. DSCK -- PCS to SCK Delay 0 = PCS valid to SCK transition is one-half SCK. 1 = SPCR1 DSCKL[6:0] field specifies delay from PCS valid to SCK. PCS[3:0] -- Peripheral Chip Select Use peripheral chip-select bits to select an external device for serial data transfer. More than one peripheral chip select can be activated at a time, and more than one peripheral chip can be connected to each PCS pin, provided that proper fanout is observed. 7.4.4 Operating Modes The QSPI operates in either master or slave mode. Master mode is used when the MCU originates data transfers. Slave mode is used when an external device initiates serial transfers to the MCU through the QSPI. Switching between the modes is controlled by MSTR in SPCR0. Before entering either mode, appropriate QSM and QSPI registers must be properly initialized.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 113
In master mode, the QSPI executes a queue of commands defined by control bits in each command RAM queue entry. Chip-select pins are activated, data is transmitted from transmit RAM and received into receive RAM. In slave mode, operation proceeds in response to SS pin activation by an external bus master. Operation is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. When the QSPI is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. Although the QSPI inherently supports multi-master operation, no special arbitration mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being set, nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be disabled by clearing SPE in SPCR1. 7.5 SCI Submodule The SCI submodule is used to communicate with external devices through an asynchronous serial bus. The SCI is fully compatible with the SCI systems found on other Motorola MCUs, such as the M68HC11 and M68HC05 Families. 7.5.1 SCI Pins There are two unidirectional pins associated with the SCI. The SCI controls the transmit data (TXD) pin when enabled, whereas the receive data (RXD) pin remains a dedicated input pin to the SCI. TXD is available as a general-purpose I/O pin when the SCI transmitter is disabled. When used for I/O, TXD can be configured either as input or output, as determined by QSM register DDRQS. Table 60 shows SCI pins and their functions. Table 60 SCI Pins
Pin Names Receive Data Transmit Data Mnemonics RXD TXD Mode Receiver Disabled Receiver Enabled Transmitter Disabled Transmitter Enabled Function Not Used Serial Data Input to SCI General-Purpose I/O Serial Data Output from SCI
7.5.2 SCI Registers The SCI programming model includes QSM global and pin control registers, and four SCI registers. There are two SCI control registers, one status register, and one data register. All registers can be read or written at any time by the CPU. Changing the value of SCI control bits during a transfer operation may disrupt operation. Before changing register values, allow the transmitter to complete the current transfer, then disable the receiver and transmitter. Status flags in the SCSR may be cleared at any time.
MOTOROLA 114
MC68HC916X1 MC68HC916X1TS/D
SCCR0 -- SCI Control Register 0
15 0 0 14 0 0 13 0 0 12 11 10 9 8 7 SCBR[12:0] 0 6 5 4 3 2
$YFFC08
1 0
RESET:
0
0
0
0
0
0
0
0
0
1
0
0
SCCR0 contains a baud rate selection parameter. Baud rate must be set before the SCI is enabled. The CPU can read and write this register at any time. Bits [15:13] -- Not Implemented SCBR[12:0] -- Baud Rate SCI baud rate is programmed by writing a 13-bit value to BR. The baud rate is derived from the MCU system clock by a modulus counter. The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud rate generator produces a receiver sampling clock with a frequency 16 times that of the expected baud rate of the incoming data. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. Receiver sampling rate is always 16 times the frequency of the SCI baud rate, which is calculated as follows: System Clock SCI Baud Rate = ------------------------------------------32 x SCBR[12:0] or System Clock SCBR[12:0] = -------------------------------------------------------------------------32 x SCI Baud Rate Desired where SCBR[12:0] is in the range {1, 2, 3, ..., 8191} Writing a value of zero to SCBR[12:0] disables the baud rate generator. Table 61 lists the SCBR[12:0] settings for standard and maximum baud rates using a 16.78 MHz system clock. Table 61 SCI Baud Rates
Nominal Baud Rate 64 110 300 600 1200 2400 4800 9600 19200 38400 76800 Maximum Rate Actual Rate with 16.78 MHz Clock 64.0 110.0 300.0 600.1 1200.1 2400.3 4800.5 9601.1 18802.1 37604.2 75208.3 451250.0 SCBR[12:0] Value $1B8B $1006 $05E0 $02F0 $0178 $00BC $005E $002F $0018 $000C $0006 $0001
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 115
SCCR1 -- SCI Control Register 1
15 0 0 LOOPS WOMS 0 0 14 13 ILT 0 12 PT 0 11 PE 0 10 M 0 9 WAKE 0 8 TIE 0 7 TCIE 0 6 RIE 0 5 ILIE 0 4 TE 0 3 RE 0 2
$YFFC0A
RWU 0 1 SBK 0 0
RESET:
SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any time. The SCI can modify RWU in some circumstances. In general, interrupts enabled by these control bits are cleared by reading SCSR, then reading (for receiver status bits) or writing (for transmitter status bits) SCDR. Bit 15 -- Not Implemented LOOPS -- Loop Mode 0 = Normal SCI operation, no looping, feedback path disabled 1 = Test SCI operation, looping, feedback path enabled LOOPS controls a feedback path on the data serial shifter. When loop mode is enabled, SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver must be enabled before entering loop mode. WOMS -- Wired-OR Mode for SCI Pins 0 = If configured as an output, TXD is a normal CMOS output. 1 = If configured as an output, TXD is an open-drain output. WOMS determines whether the TXD pin is an open-drain output or a normal CMOS output. This bit is used only when TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect. ILT -- Idle-Line Detect Type 0 = Short idle-line detect (start count on first one) 1 = Long idle-line detect (start count on first one after stop bit(s)) PT -- Parity Type 0 = Even parity 1 = Odd parity When parity is enabled, PT determines whether parity is even or odd for both the receiver and the transmitter. PE -- Parity Enable 0 = SCI parity disabled 1 = SCI parity enabled PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the received parity bit is not correct, the SCI sets the PF error flag in SCSR. When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which results in either seven or eight bits of user data, depending on the condition of M bit. Table 62 lists the available choices. Table 62 Parity Enable Data Bit Selection
M 0 0 1 1 PE 0 1 0 1 Result 8 Data Bits 7 Data Bits, 1 Parity Bit 9 Data Bits 8 Data Bits, 1 Parity Bit
MOTOROLA 116
MC68HC916X1 MC68HC916X1TS/D
M -- Mode Select 0 = SCI frame: 1 start bit, 8 data bits, 1 stop bit (10 bits total) 1 = SCI frame: 1 start bit, 9 data bits, 1 stop bit (11 bits total) WAKE -- Wakeup by Address Mark 0 = SCI receiver awakened by idle-line detection 1 = SCI receiver awakened by address mark (last bit set) TIE -- Transmit Interrupt Enable 0 = SCI TDRE interrupts inhibited 1 = SCI TDRE interrupts enabled TCIE -- Transmit Complete Interrupt Enable 0 = SCI TC interrupts inhibited 1 = SCI TC interrupts enabled RIE -- Receiver Interrupt Enable 0 = SCI RDRF interrupt inhibited 1 = SCI RDRF interrupt enabled ILIE -- Idle-Line Interrupt Enable 0 = SCI IDLE interrupts inhibited 1 = SCI IDLE interrupts enabled TE -- Transmitter Enable 0 = SCI transmitter disabled (TXD pin may be used as I/O) 1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter) The transmitter retains control of the TXD pin until completion of any character transfer that was in progress when TE is cleared. RE -- Receiver Enable 0 = SCI receiver disabled (status bits inhibited) 1 = SCI receiver enabled RWU -- Receiver Wakeup 0 = Normal receiver operation (received data recognized) 1 = Wakeup mode enabled (received data ignored until awakened) Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver status flags are not set, and interrupts are inhibited. This bit is cleared automatically (returned to normal mode) when the receiver is awakened. SBK -- Send Break 0 = Normal operation 1 = Break frame(s) transmitted after completion of current frame SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared. If SBK is toggled (one to zero in less than one frame interval), the transmitter sends only one or two break frames before reverting to idle line or beginning to send data.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 117
SCSR -- SCI Status Register
15 14 13 NOT USED 12 11 10 9 TDRE 1 8 TC 1 7 RDRF 0 6 RAF 0 5 IDLE 0 4 OR 0 3 NF 0 2
$YFFC0C
FE 0 1 PF 0 0
RESET:
SCSR contains flags that show SCI operational conditions. These flags can be cleared either by hardware or by a special acknowledgment sequence. The sequence consists of SCSR read with flags set, followed by SCDR read (write in the case of TDRE and TC). A long-word read can consecutively access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits, but before the CPU has written or read register SCDR, the newly set status bit is not cleared. SCSR must be read again with the bit set. Also, SCDR must be written or read before the status bit is cleared. Reading either byte of SCSR causes all 16 bits to be accessed. Any status bit already set in either byte will be cleared on a subsequent read or write of register SCDR. TDRE -- Transmit Data Register Empty Flag 0 = Register TDR still contains data to be sent to the transmit serial shifter. 1 = A new character can now be written to the transmit data register. TDRE is set when the byte in the transmit data register is transferred to the transmit serial shifter. If TDRE is zero, transfer has not occurred and a write to the transmit data register will overwrite the previous value. New data is not transmitted if the transmit data register is written without first clearing TDRE. TC -- Transmit Complete Flag 0 = SCI transmitter is busy 1 = SCI transmitter is idle TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or queued breaks (logic zero). The interrupt can be cleared by reading SCSR when TC is set and then by writing the transmit data register of SCDR. RDRF -- Receive Data Register Full Flag 0 = Receive data register is empty or contains previously read data. 1 = Receive data register contains new data. RDRF is set when the content of the receive serial shifter is transferred to the receive data register. If one or more errors are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle. RAF -- Receiver Active Flag 0 = SCI receiver is idle 1 = SCI receiver is busy RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in systems with multiple masters. IDLE -- Idle-Line Detected Flag 0 = SCI receiver did not detect an idle-line condition. 1 = SCI receiver detected an idle-line condition. IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF is set when a break is received, so that a subsequent idle line can be detected.
MOTOROLA 118
MC68HC916X1 MC68HC916X1TS/D
OR -- Overrun Error Flag 0 = RDRF is cleared before new data arrives. 1 = RDRF is not cleared before new data arrives. OR is set when a new byte is ready to be transferred from the receive serial shifter to the receive data register, and RDRF is still set. Data transfer is inhibited until OR is cleared. Previous data in receive data register remains valid, but data received during overrun condition (including the byte that set OR) is lost. NF -- Noise Error Flag 0 = No noise detected on the received data 1 = Noise occurred on the received data NF is set when the SCI receiver detects noise on a valid start bit, on any data bit, or on a stop bit. It is not set by noise on the idle line or on invalid start bits. Each bit is sampled three times. If none of the three samples are the same logic level, the majority value is used for the received data value, and NF is set. NF is not set until an entire frame is received and RDRF is set. FE -- Framing Error Flag 0 = No framing error on the received data. 1 = Framing error or break occurred on the received data. FE is set when the SCI receiver detects a zero where a stop bit was to have occurred. FE is not set until the entire frame is received and RDRF is set. A break can also cause FE to be set. It is possible to miss a framing error if RXD happens to be at logic level one at the time the stop bit is expected. PF -- Parity Error Flag 0 = No parity error on the received data 1 = Parity error occurred on the received data PF is set when the SCI receiver detects a parity error. PF is not set until the entire frame is received and RDRF is set. SCDR -- SCI Data Register
15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 R8/T8 U 8 R7/T7 U 7 R6/T6 U 6 R5/T5 U 5 R4/T4 U 4 R3/T3 U 3 R2/T2 U 2
$YFFC0E
R1/T1 U 1 R0/T0 U 0
RESET:
SCDR contains two data registers at the same address. The receive data register is a read-only register that contains data received by the SCI. The data comes into the receive serial shifter and is transferred to the receive data register. The transmit data register is a write-only register that contains data to be transmitted. The data is first written to the transmit data register, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/ T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 119
8 Standby RAM Module
The standby RAM module (SRAM) provides 2 Kbytes of fast RAM that is especially useful for system stacks and variable storage. The SRAM has a dedicated power supply pin so that memory content can be preserved when the MCU is powered down. 8.1 Overview The SRAM module consists of a control register block that is located at a fixed range of addresses in MCU address space, and a 2 Kbyte array of two bus cycle static RAM that can be mapped to any 2 Kbyte boundary in MCU address space. SRAM control registers are located at addresses $YFFB00-YFFB08. The module responds to program and data space accesses. Data can be read or written in bytes, words, or long words. The RAM array must not be mapped so that array addresses overlap module control register addresses, as overlap makes the registers inaccessible. SRAM is powered by VDD in normal operation. During power-down, SRAM contents are maintained by power from the VSTBY input. Power switching between sources is automatic. Table 63 shows the SRAM address map.
Table 63 SRAM Address Map
Address $YFFB001 $YFFB02 $YFFB04 $YFFB06 15 87 RAM MODULE CONFIGURATION REGISTER (RAMMCR) RAM TEST REGISTER (RAMTST) RAM ARRAY BASE ADDRESS REGISTER HIGH (RAMBAH) RAM ARRAY BASE ADDRESS REGISTER LOW (RAMBAL) 0
1. Y = M111, where M is the logic state of the module mapping (MM) bit in SCIMCR.
8.2 SRAM Register Block There are four SRAM control registers: the SRAM module configuration register (RAMMCR), the SRAM test register (RAMTST), and the SRAM array base address registers (RAMBAH/RAMBAL). 8.3 SRAM Registers SRAM responds to both program and data space accesses based on the value in the RASP field in RAMMCR. This allows code to be executed from RAM. RAMMCR -- RAM Module Configuration Register
STOP 1 15 14 0 0 13 0 0 12 0 0 RLCK 0 11 10 0 0 9 RASP[1:0] 8 7 6 5 NOT USED 0 0 4 3 2
$YFFB00
1 0
RESET:
1
1
0
0
0
0
0
0
Use RAMMCR to determine whether the RAM is in STOP mode or normal mode. RAMMCR can determine in which space the array resides and also controls access to the base array registers. Reads of unimplemented bits always return zeros. Writes do not affect unimplemented bits.
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STOP -- Stop Control 0 = RAM array operates normally. 1 = RAM array enters low-power stop mode. This bit controls whether the RAM array is in stop mode or normal operation. Reset state is one, leaving the array configured for LPSTOP operation. In stop mode, the array retains its contents, but cannot be read or written by the CPU. This bit can be read or written at any time. RLCK -- RAM Base Address Lock 0 = SRAM base address registers can be written from IMB 1 = SRAM base address registers are locked RLCK defaults to zero on reset. It can be written to one once. RASP[1:0] -- RAM Array Space This field limits access to the SRAM array in microcontrollers that support separate user and supervisor operating modes. Because the CPU16 operates in supervisor mode only, RASP1 has no effect. Refer to Table 64. Table 64 RASP Encoding
RASP X0 X1 Space Program and Data Program
RAMTST -- RAM Test Register
$YFFB02
RAMTST is for factory test only. Reads of this register return zeros and writes have no effect. RAMBAH -- Array Base Address Register High
15 14 13 NOT USED 12 11 10 9 8 ADDR 23 0 7 ADDR 22 0 6 ADDR 21 0 5 ADDR 20 0 4 ADDR 19 0 3 ADDR 18 0 2
$YFFB04
ADDR 17 0 1 ADDR 16 0 0
RESET:
RAMBAL -- Array Base Address Register Low
ADDR 15 0 15 ADDR 14 0 14 ADDR 13 0 13 ADDR 12 0 12 ADDR 11 0 11 10 9 8 7 6 NOT USED 5 4 3 2
$YFFB06
1 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
RAMBAH and RAMBAL specify an SRAM base address in the system memory map. They can only be written while the SRAM is in low-power mode (RAMMCR STOP = 1, the default out of reset) and the base address lock is disabled (RAMMCR RLCK = 0, the default out of reset). This prevents accidental remapping of the array. Because the CPU16 drives ADDR[23:20] to the same logic level as ADDR19, the values of the RAMBAH ADDR[23:20] fields must match the value of the ADDR19 field for the array to be accessible.
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8.4 SRAM Operation There are five SRAM operating modes. They include the following: 1. The RAM module is in normal mode when powered by VDD. The array can be accessed by byte, word, or long word. A byte or aligned word (high-order byte is at an even address) access only takes one bus cycle or two system clocks. A long word or misaligned word access requires two bus cycles. 2. Standby mode is intended to preserve RAM contents when VDD is removed. SRAM contents are maintained by a power source connected to the VSTBY pin. The standby voltage is referred to as VSB. Circuitry within the SRAM module switches to the higher of VDD or VSB with no loss of data. When SRAM is powered from the VSTBY pin, access to the array is not guaranteed. If standby operation is not desired, connect the VSTBY pin to VSS. 3. Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous reset occurs while a byte or word SRAM access is in progress, the access is completed. If reset occurs during the first word access of a long-word operation, only the first word access is completed. If reset occurs during the second word access of a long word operation, the entire access is completed. Data being read from or written to the RAM may be corrupted by asynchronous reset. 4. Test mode is used for factory testing of the RAM array. 5. Writing the STOP bit of RAMMCR causes the SRAM module to enter stop mode. The RAM array is disabled which, if necessary, allows external logic to decode SRAM addresses but all data is retained. If VDD falls below VSB, internal circuitry switches to VSB, as in standby mode. Exit the stop mode by clearing the STOP bit.
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9 Flash EEPROM Module
The MC68HC916X1 contains two flash electrically erasable programmable read-only memory (EEPROM) modules: a 16 Kbyte module and a 32 Kbyte module. 9.1 Overview The flash EEPROM modules serve as nonvolatile, fast-access, electrically erasable and programmable ROM-emulation memory. The modules can contain program code (e.g., operating system kernels and standard subroutines) which must execute at high speed or is frequently executed, or static data which is read frequently. The flash EEPROM supports both byte and word reads. It is capable of responding to back-to-back IMB accesses to provide two bus cycle (four system clock) access for aligned long words. It can also be programmed to insert up to three wait states to accommodate migration from slower external development memory to onboard flash EEPROM without the need for retiming the system. The 16 Kbyte flash EEPROM array can begin on any 16 Kbyte boundary, and the 32 Kbyte array can begin on any 32 Kbyte boundary. The two arrays can be configured to appear as a single contiguous memory block, with the 16 Kbyte array immediately preceding or immediately following the 32 Kbyte array. Pulling data bus pin DATA14 low during reset disables both the 16- and 32-Kbyte flash EEPROM modules and places them in stop mode. Either of the flash EEPROM modules can be configured to generate bootstrap information on system reset. Bootstrap information consists of the initial program counter and stack pointer values for the CPU16. The flash EEPROM and its control bits are erasable and programmable under software control. Program/erase voltage must be supplied via external VFPE pins. Data is programmed in byte or word aligned fashion. Multiple word programming is not supported. The flash EEPROM modules support bulk erase only, and have a minimum program-erase life of 100 cycles. The flash EEPROM modules have hardware interlocks which protect stored data from corruption by accidental enabling of the program/erase voltage to the flash EEPROM arrays. With the hardware interlocks, inadvertent programming or erasure is highly unlikely. 9.2 Address Map Table 65 shows the flash EEPROM module address map.
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Table 65 Flash EEPROM Address Map
Address $YFF8001 $YFF802 $YFF804 $YFF806 $YFF808 $YFF80A $YFF80C $YFF80E $YFF810 $YFF812 $YFF814 $YFF816 $YFF818 $YFF81A $YFF81C $YFF81E $YFF820 $YFF822 $YFF824 $YFF826 $YFF828 $YFF82A $YFF82C $YFF82E $YFF830 $YFF832 $YFF834 $YFF836 $YFF838 $YFF83A $YFF83C $YFF83E Register FLASH EEPROM MODULE CONFIGURATION (FEE1MCR) FLASH EEPROM TEST REGISTER (FEE1TST) FLASH EEPROM BASE ADDRESS HIGH (FEE1BAH) FLASH EEPROM BASE ADDRESS LOW (FEE1BAL) FLASH EEPROM CONTROL REGISTER (FEE1CTL) RESERVED RESERVED RESERVED FLASH EEPROM BOOTSTRAP WORD 0 (FEE1BS0) FLASH EEPROM BOOTSTRAP WORD 1 (FEE1BS1) FLASH EEPROM BOOTSTRAP WORD 2 (FEE1BS2) FLASH EEPROM BOOTSTRAP WORD 3 (FEE1BS3) RESERVED RESERVED RESERVED RESERVED FLASH EEPROM MODULE CONFIGURATION (FEE2MCR) FLASH EEPROM TEST REGISTER (FEE2TST) FLASH EEPROM BASE ADDRESS HIGH (FEE2BAH) FLASH EEPROM BASE ADDRESS LOW (FEE2BAL) FLASH EEPROM CONTROL REGISTER (FEE2CTL) RESERVED RESERVED RESERVED FLASH EEPROM BOOTSTRAP WORD 0 (FEE2BS0) FLASH EEPROM BOOTSTRAP WORD 1 (FEE2BS1) FLASH EEPROM BOOTSTRAP WORD 2 (FEE2BS2) FLASH EEPROM BOOTSTRAP WORD 3 (FEE2BS3) RESERVED RESERVED RESERVED RESERVED 32 KBYTE FLASH EEPROM Module 16 KBYTE FLASH EEPROM
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIMCR.
9.3 Flash EEPROM Control Block Each flash EEPROM module has a 32 byte control block with five registers to control flash EEPROM operation: the flash EEPROM module configuration register (FEE1MCR, FEE2MCR), the flash EEPROM test register (FEE1TST, FEE2TST), the flash EEPROM array base address registers (FEE1BAH, FEE2BAH, and FEE1BAL, FEE2BAL), and the flash EEPROM control register (FEE1CTL, FEE2CTL). Four additional flash EEPROM words in the control block can contain bootstrap information for use during reset. Control registers are located in supervisor data space.
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The control register blocks for the 16 Kbyte and 32 Kbyte flash EEPROM modules start at locations $YFF800 and $YFF820, respectively. The following register descriptions apply to the corresponding register in either control block. References to FEExMCR, for example, apply to both FEE1MCR (in the 16 Kbyte module) and FEE2MCR (in the 32 Kbyte module.) A number of control register bits have associated bits in "shadow" registers. The values of the shadow bits determine the reset states of the control register bits. Shadow registers are programmed or erased in the same manner as a location in the array, using the address of the corresponding control registers. When a shadow register is programmed, the data is not written to the corresponding control register. The new data is not copied into the control register until the next reset. The contents of shadow registers are erased when the array is erased. Configuration information is specified and programmed independently of the array. After reset, registers in the control block that contain writable bits can be modified. Writes to these registers do not affect the associated shadow register. Certain registers can be written only when LOCK = 0 or STOP = 1 in FEExMCR. 9.4 Flash EEPROM Array The base address registers specify the starting address of the flash EEPROM array. The user programs the reset base address. The base address of the 16 Kbyte array must be on a 16 Kbyte boundary; the base address of the 32 Kbyte array must be on a 32 Kbyte boundary. Behavior will be indeterminate if one flash EEPROM array overlaps the other. The base address must also be set so that an array does not overlap a flash EEPROM control block in the data space memory map. If an array does overlap a control block, accesses to the 32 bytes in the array that is overlapped are ignored, allowing the flash EEPROM control blocks to remain accessible. If the array overlaps the control block of another module, the results will be indeterminate. 9.5 Flash EEPROM Registers In the following register diagrams, bits with reset states determined by shadow bits are shaded, and the reset state is annotated "SB". FEE1MCR, FEE2MCR -- Flash EEPROM Module Configuration Registers
STOP 15 FRZ 0 14 13 0 0 BOOT SB 12 LOCK SB 11 10 0 0 9 ASPC[1:0] 8 7 WAIT[1:0] 6 5 0 0 4 0 0 3 0 0
$YFF800, $YFF820
2 0 0 1 0 0 0 0 0
RESET:
DATA14 + SB
SB
SB
SB
SB
The flash EEPROM module configuration registers (FEE1MCR, FEE2MCR) control module configuration. This register can be written only when LOCK = 0. All active bits in the FEExMCR take values from the associated shadow register during reset. STOP -- Stop Mode Control 0 = Normal operation 1 = Low-power stop operation STOP can be set either by pulling data bus pin DATA14 low during reset (for both flash EEPROM modules) or by the corresponding shadow bit. The array can be re-enabled by clearing STOP. If STOP is set during programming or erasing, the program/erase voltage is automatically turned off. However, the ENPE control bit in FEExCTL remains set. When STOP is cleared, the program/erase voltage is automatically turned back on if ENPE is set.
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FRZ -- Freeze Mode Control 0 = Disable program/erase voltage while FREEZE is asserted 1 = Allow ENPE bit to turn on the program/erase voltage while FREEZE is asserted BOOT -- Boot Control 0 = Flash EEPROM module responds to bootstrap addresses after reset 1 = Flash EEPROM module does not respond to bootstrap addresses after reset On reset, BOOT takes on the value stored in its associated shadow bit. If BOOT = 0 and STOP = 0, the module responds to program space accesses to IMB addresses $000000 to $000006 following reset, and the contents of FEExBS[3:0] are used as bootstrap vectors. After address $000006 is read, the module responds normally to control block or array addresses only. LOCK -- Lock Registers 0 = Write-locking disabled 1 = Write-locked registers protected If the reset state of LOCK is zero, it can be set once after reset to allow protection of the registers after initialization. Once the LOCK bit is set by software, it cannot be cleared again until after a reset. ASPC[1:0] -- Flash EEPROM Array Space ASPC[1:0] assigns the array to supervisor or user space, and to program or data space. The state of ASPC[1:0] out of reset is determined by the value stored in the associated shadow bits. Since the CPU16 runs only in supervisor mode, ASPC1 must remain set to one for array accesses to take place. The field can be written only when LOCK = 0 and STOP = 1. Refer to Table 66. Table 66 Array Space Encoding
ASPC[1:0] 10 11 Type of Access Supervisor program and data space Supervisor program space
WAIT[1:0] -- Wait States The state of WAIT[1:0] out of reset is determined by the value stored in the associated shadow bits. WAIT[1:0] specifies the number of wait states inserted during accesses to the flash EEPROM module. A wait state has the duration of one system clock cycle. WAIT[1:0] affects both control block and array accesses, and can be written only if LOCK = 0 and STOP = 1. Refer to Table 67. Table 67 Wait State Encoding
WAIT[1:0] 00 01 10 11 Wait States 0 1 2 -1 Clocks Per Transfer 3 4 5 2
The value of WAIT[1:0] is compatible with the lower two bits of the DSACK field in the SCIM chip-select option registers. An encoding of %11 in WAIT[1:0] corresponds to an encoding for fast termination. FEE1TST, FEE2TST -- Flash EEPROM Test Registers These registers are used for factory test only. $YFF802, $YFF822
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FEE1BAH, FEE2BAH -- Flash EEPROM Base Address High Registers
15 0 14 0 13 0 12 0 11 0 10 0 0 9 0 8 ADDR 23 SB 7 ADDR 22 SB 6 ADDR 21 SB 5 ADDR 20 SB 4 ADDR 19 SB 3
$YFF804, $YFF824
ADDR 18 SB 2 ADDR 17 SB 1 ADDR 16 SB 0
0
RESET:
0
0
0
0
0
0
0
FEE1BAL -- Flash EEPROM Base Address Low Register
ADDR 15 SB 15 ADDR 14 SB 14 13 0 12 0 11 0 10 0 0 9 0 8 0 7 0 6 5 0 0 4 3 0 2 0
$YFF806
1 0 0 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FEE2BAL -- Flash EEPROM Base Address Low Register
15 0 14 0 13 0 12 0 11 0 10 0 0 9 0 8 7 0 0 6 0 0 5 0 4 0 0 3 0 2 0
$YFF826
1 0 0 0
SB
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
The base address high registers (FEE1BAH, FEE2BAH) contain the 8 high-order bits of the array base address; the base address low registers (FEE1BAL, FEE2BAL) contain the active low-order bits of the array base address. During reset, both FEExBAH and FEExBAL take on default values programmed into associated shadow registers. After reset, if LOCK = 0 and STOP = 1, software can write to FEExBAH and FEExBAL to relocate the array. FEE1CTL, FEE2CTL -- Flash EEPROM Control Register
15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 VFPE 0 3
$YFF808, $YFF828
ERAS 0 2 LAT 0 1 ENPE 0 0
RESET:
The flash EEPROM control registers (FEE1CTL, FEE2CTL) control programming and erasure of the arrays. FEExCTL is accessible in supervisor mode only. VFPE -- Verify Program/Erase 0 = Normal read cycles 1 = Invoke program verify circuit The VFPE bit invokes a special program-verify circuit. During programming sequences (ERAS = 0), VFPE is used in conjunction with the LAT bit to determine when programming of a location is complete. If VFPE and LAT are both set, a bit-wise exclusive-OR of the latched data with the data in the location being programmed occurs when any valid FLASH location is read. If the location is completely programmed, a value of zero is read. Any other value indicates that the location is not fully programmed. When VFPE is cleared, normal reads of valid FLASH locations occur. The value of VFPE cannot be changed while ENPE = 1. ERAS -- Erase Control 0 = Flash EEPROM configured for programming 1 = Flash EEPROM configured for erasure The ERAS bit configures the array for either programming or erasure. Setting ERAS causes all locations in the array and all control bits in the control block to be configured for erasure at the same time. When the LAT bit is set, ERAS also determines whether a read returns the data in the addressed location (ERAS = 1) or the address itself (ERAS = 0). ERAS cannot be changed while ENPE = 1.
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LAT -- Latch Control 0 = Programming latches disabled 1 = Programming latches enabled The LAT bit configures the EEPROM array for normal reads or for programming. When LAT is cleared, the FLASH module address and data buses are connected to the IMB address and data buses and the module is configured for normal reads. When LAT is set, module address and data buses are connected to parallel internal latches and the array is configured for programming or erasing. Once LAT is set, the next write to a valid FLASH module address causes the programming circuitry to latch both address and data. Unless control register shadow bits are to be programmed, the write must be to an array address. The value of LAT cannot be changed while ENPE = 1. ENPE -- Enable Programming/Erase 0 = Disable program/erase voltage 1 = Apply program/erase voltage to flash EEPROM Setting the ENPE bit applies the program/erase voltage to the array. ENPE can be set only after LAT has been set and a write to the data and address latches has occurred. ENPE remains cleared if these conditions are not met. While ENPE is set, the LAT, VFPE, and ERAS bits cannot be changed, and attempts to read an array location are ignored. FEE1BS[3:0] -- Flash EEPROM Bootstrap Words FEE2BS[3:0] -- Flash EEPROM Bootstrap Words $YFF810-$YFF816 $YFF830-$YFF836
The flash EEPROM bootstrap words (FEE1BS[3:0], FEE2BS[3:0]) can be used as system bootstrap vectors. When BOOT = 1 in FEExMCR during reset, the flash module responds to program space accesses of IMB addresses $000000 to $000006 after reset. When BOOT = 0, the flash module responds only to normal array and register accesses. FEExBS[3:0] can be read at any time, but it can only be changed by programming the appropriate locations. Table 68 shows bootstrap word addresses in program space. Table 68 Bootstrap Words
Bootstrap Word FEE1BS0, FEE2BS0 FEE1BS1, FEE2BS1 FEE1BS2, FEE2BS2 FEE1BS3, FEE2BS3 Corresponding Boot Address $000000 $000002 $000004 $000006 Corresponding Vector Content Initial ZK, SK, and PC Initial PC Initial SP Initial IZ
9.6 Flash EEPROM Operation The following paragraphs describe the operation of the flash EEPROM module during reset, system boot, normal operation, and while it is being programmed or erased. 9.6.1 Reset Operation Reset initializes all registers to certain default values. Some of these reset values are programmable by the user and are contained in flash EEPROM shadow registers. If the state of the STOP shadow bit is zero, and bus pin DATA14 is pulled high during reset, the STOP bit in the FEExMCR is cleared during reset. The array responds normally to the bootstrap address range and the flash EEPROM array base address. If the STOP shadow bit is one, or the module's associated data bus pin is pulled low during reset, the STOP bit in the FEExMCR is set. The flash EEPROM array is disabled until the STOP bit is cleared by software. It will not respond to the bootstrap address range, or the flash EEPROM array base address in FEExBAH and FEExBAL, allowing an external device to respond to the flash EEPROM array's address space or bootstrap information. Since the erased state of the shadow bits is one, erased flash EEPROM modules (which include the shadow registers in the control blocks) come out of reset in STOP mode.
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9.6.2 Bootstrap Operation After reset, the CPU begins bootstrap operation by fetching initial values for its internal registers from special bootstrap word addresses $000000 through $000006. If BOOT = 0 and STOP = 0 in FEExMCR, the flash EEPROM module is configured to recognize these addresses after a reset and provide this information from the FEExBS[3:0] bootstrap registers in the flash EEPROM control block. The information in these registers is programmed by the user. 9.6.3 Normal Operation The flash EEPROM module allows a byte or aligned-word read in one bus cycle. Long-word reads require two bus cycles. The module checks function codes to verify access privileges. All control block addresses must be in supervisor data space. Array accesses are defined by the state of ASPC[1:0] in FEExMCR. Access time is governed by the WAIT[1:0] field in FEExMCR. Accesses to any address in the address block defined by FEExBAH and FEExBAL which does not fall within the array are ignored, allowing external devices to adjoin flash EEPROM arrays which do not entirely fill the entire address space specified by FEExBAH and FEExBAL. 9.6.4 Program/Erase Operation An erased flash bit has a logic state of one. A bit must be programmed to change its state from one to zero. Erasing a bit returns it to a logic state of one. Programming and erasing the flash module requires a series of control register writes and a write to an array address. The same procedure is used to program control registers that contain flash shadow bits. Programming is restricted to a single byte or aligned word at a time. The entire array and the shadow register bits are erased at the same time. When multiple flash modules share a single VFPE pin, do not program or erase more than one flash module at a time. Normal accesses to modules that are not being programmed are not affected by programming or erasure of another flash module. The following paragraphs give step-by-step procedures for programming and erasure of flash EEPROM arrays. Refer to 11 Electrical Characteristics for information on programming and erasing specifications for the flash EEPROM module. 9.6.4.1 Programming The following steps are used to program a flash EEPROM array. Figure 22 is a flowchart of the programming operation. Refer to Figures 45 and 46 in 11 Electrical Characteristics for VFPE to VDD relationships during programming. 1. Increase voltage applied to the VFPE pin to program/erase/verify level. 2. Clear the ERAS bit and set the LAT bit in FEExCTL. This enables the programming address and data latches. 3. Write data to the address to be programmed. This latches the address to be programmed and the programming data. 4. Set the ENPE bit in FEExCTL. This starts the program pulse. 5. Delay the proper amount of time for one programming pulse to take place. Delay is specified by parameter pwpp. 6. Clear the ENPE bit in FEExCTL. This stops the program pulse. 7. Delay while high voltage to array is turned off. Delay is specified by parameter tpr. 8. Read the address to verify that it has been programmed. 9. If the location is not programmed, repeat steps 4 through 7 until the location is programmed, or until the specified maximum number of program pulses has been reached. Maximum number of pulses is specified by parameter npp.
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10. If the location is programmed, repeat the same number of pulses as required to program the location. This provides 100% program margin. 11. Read the address to verify that it remains programmed. 12. Clear the LAT bit in FEExCTL. This disables the programming address and data latches. 13. If more locations are to be programmed, repeat steps 2 through 10. 14. Reduce voltage applied to the VFPE pin to normal read level. 9.6.4.2 Erasure The following steps are used to erase a flash EEPROM array. Figure 23 is a flowchart of the erasure operation. Refer to Figures 45 and 46 in 11 Electrical Characteristics for VFPE to VDD relationships during erasure. 1. Increase voltage applied to the VFPE pin to program/erase/verify level. 2. Set the ERAS bit and the LAT bit in FEExCTL. This configures the module for erasure. 3. Perform a write to any valid address in the control block or array. The data written does not matter. 4. Set the ENPE bit in FEExCTL. This applies the erase voltage to the array. 5. Delay the proper amount of time for one erase pulse. Delay is specified by parameter tepk. 6. Clear the ENPE bit in FEExCTL. This turns off erase voltage to the array. 7. Delay while high voltage to array is turned off. Delay is specified by parameter ter. 8. Read the entire array and control block to ensure all locations are erased. 9. If all locations are not erased, calculate a new value for tepk (tei x pulse number) and repeat steps 3 through 10 until all locations erase, or the maximum number of pulses has been applied. 10. If all locations are erased, calculate the erase margin (em) and repeat steps 3 through 10 for the single margin pulse. 11. Clear the LAT and ERAS bits in FEExCTL. This allows normal access to the flash. 12. Reduce voltage applied to the VFPE pin to normal read level.
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INCREASE VFPE TO 1 PROGRAM/ERASE/VERIFY LEVEL CLEAR npp COUNTER, CLEAR MARGIN FLAG SET LAT, CLEAR ERAS WRITE DATA TO ADDRESS SET ENPE START PROGRAM PULSE TIMER (pwpp) DELAY FOR pwpp CLEAR ENPE, START tpr TIMER DELAY FOR tpr INCREMENT ADDRESS
2 3
N
npp = 0 ?
Y
READ LOCATION TO VERIFY
MARGIN FLAG SET ?
Y
DECREMENT npp COUNTER DATA CORRECT ?
INCREMENT npp COUNTER, READ LOCATION TO VERIFY
N
Y
CLEAR LAT
4
N
DONE PROGRAMMING
N
DATA CORRECT ?
N
Y
SET MARGIN FLAG
Y
npp COUNTER = 50 ?
N
Y
LOCATION FAILED TO PROGRAM
NOTES: 1. SEE ELECTRICAL CHARACTERISTICS FOR VFPE PIN VOLTAGE SEQUENCING. 2. THE MARGIN FLAG IS A SOFTWARE-DEFINED FLAG THAT INDICATES WHETHER THE PROGRAM SEQUENCE IS GENERATING PROGRAM PULSES OR MARGIN PULSES. 3. TO SIMPLIFY THE PROGRAM OPERATION, THE VFPE BIT IN FEExCTL CAN BE SET. 4. CLEAR VFPE BIT ALSO IF ROUTINE USES THIS FUNCTION.
REDUCE VFPE TO 1 NORMAL READ LEVEL, EXIT PROGRAM ROUTINE
FEEPROM PGM FLOW1 TD
Figure 22 Programming Flow
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REDUCE V FPE TO 1 PROGRAM/ERASE/VERIFY LEVEL CLEAR nep COUNTER, CLEAR MARGIN FLAG SET LAT, SET ERAS WRITE TO ARRAY OR CONTROL BLOCK SET ENPE START ERASE PULSE TIMER (tepk) DELAY FOR tepk CLEAR ENPE, START tpr TIMER DELAY FOR tpr
2
MARGIN FLAG SET ? CALCULATE NEW tepk
Y
CLEAR LAT
READ ARRAY AND SHADOW REGISTERS TO VERIFY ERASE
N
ALL LOCATIONS ERASED ?
Y
CALCULATE EM, SET MARGIN FLAG
SET tepk = EM
N
INCREMENT nep COUNTER
N
nep COUNTER = 5 ?
Y
ARRAY FAILED TO ERASE REDUCE VFPE TO 1 NORMAL READ LEVEL, EXIT ERASE ROUTINE
NOTES: 1. SEE ELECTRICAL CHARACTERISTICS FOR VFPE PIN VOLTAGE SEQUENCING. 2. THE MARGIN FLAG IS A SOFTWARE-DEFINED FLAG THAT INDICATES WHETHER THE PROGRAM SEQUENCE IS GENERATING ERASE PULSES OR MARGIN PULSES.
FEEPROM PGM FLOW2 TD
Figure 23 Erasure Flow
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10 Block-Erasable Flash EEPROM
The 2 Kbyte block-erasable flash EEPROM module (BEFLASH) serves as nonvolatile, fast-access ROM-emulation memory. The module can be used for program code that must either execute at high speed or is frequently executed, such as operating system kernels and standard subroutines, or it can be used for static data that is read frequently. The module can also be configured to provide bootstrap vectors for system reset. 10.1 Overview The BEFLASH module consists of a control register block that occupies a fixed position in MCU address space and a 2 Kbyte flash EEPROM array that can be mapped to any 2 Kbyte boundary in MCU address space. The array can be configured to reside in both program and data space, or in program space alone. The flash EEPROM array can be read as either bytes, words, or long-words. The module responds to back-to-back IMB accesses, providing two bus cycle (four system clocks) access for aligned long words. The module can also be programmed to insert up to three wait states per access, to accommodate migration from slower external development memory without re-timing the system. Both the array and the individual control bits are programmable and erasable under software control. Program/erase voltage must be supplied via the external VFPE2K pin. Data is programmed in byte or word aligned fashion. The module supports both block and bulk erase modes, and has a minimum program/erase life of 100 cycles. Hardware interlocks protect stored data from corruption if the program/erase voltage to the BEFLASH EEPROM array is enabled accidently. The BEFLASH array is enabled/disabled by a combination of DATA15 and the STOP shadow bit after reset. Table 69 shows the BEFLASH address map. Table 69 BEFLASH Address Map
Address $YFF7A01 $YFF7A2 $YFF7A4 $YFF7A6 $YFF7A8 $YFF7AA $YFF7AC $YFF7AE $YFF7B0 $YFF7B2 $YFF7B4 $YFF7B6 $YFF7B8 $YFF7BA $YFF7BC $YFF7BE 15 87 0 BEFLASH MODULE CONFIGURATION REGISTER (BFEMCR) BEFLASH TEST REGISTER (BFETST) BEFLASH BASE ADDRESS HIGH REGISTER (BFEBAH) BEFLASH BASE ADDRESS LOW REGISTER (BFEBAL) BEFLASH CONTROL REGISTER (BFECTL) RESERVED RESERVED RESERVED BEFLASH BOOTSTRAP WORD 0 (BFEBS0) BEFLASH BOOTSTRAP WORD 1 (BFEBS1) BEFLASH BOOTSTRAP WORD 2 (BFEBS2) BEFLASH BOOTSTRAP WORD 3 (BFEBS3) RESERVED RESERVED RESERVED RESERVED
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIMCR.
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10.2 BEFLASH Control Block The BEFLASH module control block contains five registers: the BEFLASH module configuration register (BFEMCR), the BEFLASH test register (BFETST), the BEFLASH array base address registers (BFEBAH and BFEBAL), and the BEFLASH control register (BFECTL). Four additional words in the control block can contain bootstrap information when the BEFLASH is used as bootstrap memory. Each register in the control block has an associated shadow register that is physically located in a spare BEFLASH row. During reset, fields within the registers are loaded with default information from the shadow registers. Shadow registers are programmed or erased in the same manner as locations in the BEFLASH array, using the address of the corresponding control registers. When a shadow register is programmed, the data is not written to the corresponding control register. The new data is not copied into the control register until the next reset. The contents of shadow registers are erased whenever the BEFLASH array is erased. Configuration information is specified and programmed independently of the BEFLASH array. After reset, registers in the control block that contain writable bits can be modified. Writes to these registers do not affect the associated shadow register. Certain registers are writable only when the LOCK bit in BFEMCR is disabled or when the STOP bit in BFEMCR is set. These restrictions are noted in the individual register descriptions. 10.3 BEFLASH Array The base address registers specify the starting address of the BEFLASH array. A default base address can be programmed into the base address shadow registers. The array base address must be on a 2 Kbyte boundary. Because the states of ADDR[23:20] follow the state of ADDR19, addresses in the range $080000 to $F7FFFF cannot be accessed by the CPU16. If the BEFLASH array is mapped to these addresses, the system must be reset before the array can be accessed. Avoid using a base address value that causes the array to overlap control registers. If a portion of the array overlaps the EEPROM register block, the registers remain accessible, but accesses to that portion of the array are ignored. If the array overlaps the control block of another module, however, those registers may become inaccessible. If the BEFLASH array overlaps another memory array (RAM or flash EEPROM), proper access to one or both arrays may not be possible. 10.4 BEFLASH Registers In the following register diagrams, the reset value SB indicates that a bit assumes the value of its associated shadow bit during reset. BFEMCR -- BEFLASH Module Configuration Register
STOP 15 FRZ 0 14 13 0 0 BOOT SB 12 LOCK SB 11 10 0 0 9 ASPC[1:0] 8 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0
$YFF7A0
1 0 0 0 0 0
DATA15 + SB
RESET:
SB
SB
This register can be written only when the control block is not write-locked (when LOCK = 0). All active bits take values from the associated shadow register during reset. STOP -- Stop Mode Control 0 = Normal operation 1 = Low-power stop operation STOP can be set either by pulling data bus pin DATA15 low during reset or by the corresponding shadow bit. The EEPROM array is inaccessible during low-power stop. The array can be re-enabled by
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clearing STOP. If STOP is set during programming or erasing, the program/erase voltage is automatically turned off. However, the enable program/erase bit (ENPE) remains set. If STOP is cleared, program/erase voltage is automatically turned back on unless ENPE is cleared. FRZ -- Freeze Mode Control 0 = Disable program/erase voltage while FREEZE is asserted 1 = Allow ENPE bit to turn on the program/erase voltage while FREEZE signal is asserted BOOT -- Boot Control 0 = BEFLASH responds to bootstrap vector addresses after reset 1 = BEFLASH does not respond to bootstrap vector addresses after reset On reset, BOOT takes on the value stored in its associated shadow bit. If BOOT = 0 and STOP = 0, the module responds to program space accesses of IMB addresses $000000 to $000006 following reset, and the contents of BFEBS[3:0] are used as bootstrap vectors. After address $000006 is read, the module responds normally to control block or array addresses only. LOCK -- Lock Registers 0 = Write-locking disabled 1 = Write-locked registers protected If the reset state of the LOCK is zero, it can be set once to protect the registers after initialization. When set, LOCK cannot be cleared until reset occurs. ASPC[1:0] -- BEFLASH Array Space The CPU16 operates only in supervisory mode, and as a result, ASPC1 must remain set to one for array accesses to take place. The field can be written only if LOCK = 0 and STOP = 1. During reset, ASPC[1:0] takes on the default value programmed into the associated shadow register. Refer to Table 70. Table 70 Array Space Encoding
ASPC[1:0] 10 11 Type of Access Supervisor program and data space Supervisor program space
BFETST -- BEFLASH Test Register This register is used for factory test purposes only. BFEBAH -- BEFLASH Base Address High Register
15 14 13 NOT USED 12 11 10 9 8 ADDR 23 SB 7 ADDR 22 SB 6 ADDR 21 SB 5 ADDR 20 SB 4 ADDR 19 SB 3 ADDR 18 SB 2
$YFF7A2
$YFF7A4
ADDR 17 SB 1 ADDR 16 SB 0
RESET:
BFEBAL -- BEFLASH Base Address Low Register
ADDR 15 SB 15 ADDR 14 SB 14 ADDR 13 SB 13 ADDR 12 SB 12 ADDR 11 SB 11 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0
$YFF7A6
1 0 0 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
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BFEBAH and BFEBAL contain the 13 high-order bits of the BEFLASH array base address. During reset, BFEBAH and BFEBAL take on the default values programmed into the associated shadow registers. After reset, if LOCK = 0 and STOP = 1, software can write to BFEBAH and BFEBAL to relocate the BEFLASH array. Because the states of ADDR[23:20] follow the state of ADDR19, addresses in the range $080000 to $F7FFFF cannot be accessed by the CPU16. If the BEFLASH array is mapped to these addresses, the system must be reset before the array can be accessed. BFECTL -- BEFLASH Control Register
15 RESET: 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 VFPE 0 3 ERAS 0 2
$YFF7A8
LAT 0 1 ENPE 0 0
BFECTL contains the bits needed to control programming and erasing the BEFLASH. VFPE -- Verify Program/Erase 0 = Normal read cycles 1 = Invoke program-verify circuit This bit invokes a special program-verify circuit. During programming sequences (ERAS = 0), VFPE is used in conjunction with the LAT bit to determine when programming of a location is complete. If VFPE and LAT are both set, a bit-wise exclusive-OR of the latched data with the data in the location being programmed occurs when any valid BEFLASH location is read. If the location is completely programmed, a value of zero is read. Any other value indicates that the location is not fully programmed. When VFPE is cleared, normal reads of valid BEFLASH locations occur. ERAS -- Erase Control 0 = BEFLASH configured for programming 1 = BEFLASH configured for erasure The ERAS bit in BFECTL configures the BEFLASH array for programming or erasure. Setting ERAS causes all locations in the array and all BEFLASH shadow bits in the control block to be configured for erasure. Table 71 shows the address ranges that must be written to during an erase operation in order to erase specific blocks of the BEFLASH array. Table 71 BEFLASH Erase Operation Address Ranges
Block 0 1 2 3 4 5 6 7 Entire Array3 Addresses Affected $0000 - $007F $0080 - $0100 $0100 - $017F $0180 - $01FF $0200 - $02FF $0300 - $03FF $0400 - $05FF $0600 - $07FF Reserved $0600 - $07FF BFEBAH/ BFEBAL1 X2 Address Bits Used to Specify Block for Erasure ADDR[23:11] ADDR[10:6] ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 X 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X X X2
1. The block erasable flash base address high and low registers (BFEBAH and BFEBAL) specify ADDR[23:11] of the block to be erased. 2. These address bits are "don't cares" when specifying the block to be erased. 3. Erasing the entire array also erases the BEFLASH control register shadow bits.
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When the LAT bit is set, ERAS also determines whether a read returns the value of the addressed location (ERAS = 1) or the location being programmed (ERAS = 0). The value of ERAS cannot be changed if the program/erase voltage is turned on (ENPE = 1). LAT -- Latch Control 0 = Programming latches disabled 1 = Programming latches enabled When LAT is cleared, the BEFLASH address and data buses are connected to the IMB address and data buses. The BEFLASH is configured for normal reads. When LAT is set, the BEFLASH address and data buses are connected to parallel internal latches. The BEFLASH array is configured for programming or erasing. Once LAT is set, the next write to a valid BEFLASH address causes the programming circuitry to latch both address and data. Unless control register shadow bits are to be programmed, the write must be to an array address. The value of LAT cannot be changed when program/erase voltage is turned on (ENPE = 1). ENPE -- Enable Program/Erase 0 = Disable program/erase voltage 1 = Apply program/erase voltage ENPE can be set only after LAT has been set, and a write to the data and address latches has occurred. ENPE remains cleared if these conditions are not met. While ENPE is set, the LAT, VFPE, and ERAS bits cannot be changed, and attempts to read a BEFLASH array location in BEFLASH are ignored. BFEBS[3:0] -- BEFLASH Bootstrap Words
15 RESET: BOOTSTRAP VECTOR PROGRAMMED VALUE
$YFF7B0 - $YFF7B6
0
The BEFLASH bootstrap words (BFEBS[3:0]) can be used as system bootstrap vectors. When BOOT = 0 in BFEMCR during reset, the BEFLASH responds to program space accesses of IMB addresses $000000 to $000006 after reset. When BOOT = 1, the BEFLASH responds only to normal array and register accesses. BFEBS[3:0] can be read at any time, but the values in the words can only be changed by programming the appropriate locations. 10.5 BEFLASH Operation The following paragraphs describe the operation of the BEFLASH during reset, system boot, normal operation, and while it is being programmed or erased. 10.5.1 Reset Operation Reset initializes all BEFLASH control registers. Some bits have fixed default values, and some take values that are programmed into the associated BEFLASH shadow registers. If the state of the STOP shadow bit is zero, and data bus pin DATA15 is pulled high during reset, the STOP bit in BFEMCR is cleared during reset, and the module responds to accesses in the range specified by BFEBAH and BFEBAL. When the BOOT bit is cleared, the module also responds to bootstrap vector accesses.
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If the state of the STOP shadow bit is one, or data bus pin DATA15 is pulled low during reset, the STOP bit in BFEMCR is set during reset and the BEFLASH array is disabled. The module does not respond to array or bootstrap vector accesses until the STOP bit is cleared. This allows an external device to respond to accesses to the BEFLASH array address space or to bootstrap accesses. The erased state of the shadow bits is one. An erased module comes out of reset in STOP mode. 10.5.2 Bootstrap Operation After reset, the CPU16 begins bootstrap operation by fetching initial values for its internal registers from IMB addresses $000000 through $000006 in program space. These are the addresses of the bootstrap vectors in the exception vector table. If BOOT = 0 and STOP = 0 in BFEMCR during reset, the BEFLASH module is configured to respond to bootstrap vector accesses. Vector assignments are shown in Table 72. Table 72 Bootstrap Vector Assignments
EEPROM Bootstrap Word BFEBS0 BFEBS1 BFEBS2 BFEBS3 IMB Vector Address $000000 $000002 $000004 $000006 MCU Reset Vector Content Initial ZK, SK, and PK Initial PC Initial SP Initial IZ
As soon as address $000006 has been read, BEFLASH operation returns to normal, and the module no longer responds to bootstrap vector accesses. 10.5.3 Normal Operation The BEFLASH module allows a byte or aligned-word read in one bus cycle. Long-word reads require two bus cycles. The module checks function codes to verify address space access type. Array accesses are defined by the state of ASPC[1:0] in BFEMCR. 10.5.4 Program/Erase Operation An unprogrammed flash bit has a logic state of one. A bit must be programmed to change its state from one to zero. Erasing a bit returns it to a logic state of one. Programming or erasing the BEFLASH array requires a series of control register writes and a write to an array address. The same procedure is used to program control registers that contain flash bits. Programming is restricted to a single byte or aligned word at a time. Erasure of BEFLASH array blocks and control shadow bits are dependent on the setting of ADDR[3:1] of the address written to during an erase operation. Refer to Table 71 for the address bit patterns corresponding to specific BEFLASH blocks. NOTE In order to program the array, programming voltage must be applied to the VFPE2K pin. VFPE2K (VDD - 0.3 V) must be applied at all times or damage to the BEFLASH module can occur. Refer to 11 Electrical Characteristics for information on programming and erasing specifications for the BEFLASH module. 10.5.4.1 Programming Sequence Use the following procedure to program the BEFLASH. Refer to Figures 45 and 46 in 11 Electrical Characteristics for VFPE to VDD relationships during programming.
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1. Turn on VFPE2K (apply program/erase voltage to VFPE2K pin). 2. Clear ERAS and set LAT and VFPE bits in BFECTL to set program mode, enable programming address and data latches, and invoke special verification read circuitry. Set initial value of tppulse to tpmin. 3. Write new data to the desired address. This causes the address and data of the location to be programmed to be latched in the programming latches. 4. Set ENPE to apply programming voltage. 5. Delay long enough for one programming pulse to occur (tppulse). 6. Clear ENPE to remove programming voltage. 7. Delay while high voltage is turning off (tvprog). 8. Read the location just programmed. If the value read is all zeros, proceed to step 9. If not, calculate a new value for tppulse and repeat steps 4 through 7 until either the location is verified or the total programming time (tprogmax) has been exceeded. If tprogmax has been exceeded, the location may be bad and should not be used. 9. If the location is programmed, calculate tpmargin and repeat steps 4 through 7. If the location does not remain programmed, the location is bad. 10. Clear VFPE and LAT. 11. If there are more locations to program, repeat steps 2 through 10. 12. Turn off VFPE2K (reduce voltage on VFPE2K pin to VDD). 13. Read the entire array to verify that all locations are correct. If any locations are incorrect, the array is bad. 10.5.4.2 Erasure Sequence Use the following procedure to erase the BEFLASH. Refer to Figures 45 and 46 in 11 Electrical Characteristics for VFPE to VDD relationships during erasure. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Turn on VFPE2K (apply program/erase voltage to VFPE2K pin). Set initial value of tepulse to temin. Set LAT, VFPE, and ERAS bits to configure the BEFLASH module for erasure. Write to any valid address in the control block or array. This allows the erase voltage to be turned on. The data written and the address written to are of no consequence. Set ENPE to apply programming voltage. Delay long enough for one erase pulse to occur (tepulse). Clear ENPE to remove programming voltage. Delay while high voltage is turning off (tverase). Clear LAT, ERAS, and VFPE to allow normal access to the BEFLASH. Read the entire array and control block to ensure that the entire module is erased. If all of the locations are not erased, calculate a new value for tepulse and repeat steps 3 through 10 until either the remaining locations are erased or the maximum erase time (terasemax) has expired. If all locations are erased, calculate temargin and repeat steps 3 through 10. If all locations do not remain erased, the BEFLASH module may be bad. Turn off VFPE2K (reduce voltage on VFPE2K pin to VDD).
12. 13.
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11 Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams. Table 73 Maximum Ratings
Num 1 2 3 4 Supply Voltage1, 2, 3 Input Voltage1, 2, 3, 4, 5 Instantaneous Maximum Current Single pin limit (applies to all pins)1, 3, 5, 6 Operating Maximum Current Digital Input Disruptive Current3, 5, 5, 6, 7 VSS - 0.3 VIN VDD + 0.3 Flash EEPROM Program/Erase Supply Voltage8, 9 Operating Temperature Range C Suffix Storage Temperature Range Rating Symbol VDD Vin ID Value - 0.3 to + 6.5 - 0.3 to + 6.5 25 Unit V V mA
IID VFPE TA Tstg
- 500 to + 500 (VDD - 0.5) to +12.6 TL to TH - 40 to + 85 - 55 to + 150
A V C C
5 6 7
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. This parameter is periodically sampled rather than 100% tested. 4. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 5. All functional non-supply pins are internally clamped to VSS for transitions below VSS. All functional pins except EXTAL and XFC are internally clamped to VDD for transitions below VDD. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. 7. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. 8. VFPE must not be raised to programming level while VDD is below specified minimum value. VFPE must not be reduced below minimum specified value while VDD is applied. 9. Flash EEPROM modules can be damaged by power-on and power-off VFPE transients. Maximum power-on overshoot tolerance is 13.5 V for periods of less than 30 ns.
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Table 74 Typical Ratings
Num 1 2 Supply Voltage Operating Temperature VDD Supply Current RUN LPSTOP, VCO Off LPSTOP, External clock, max fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current VCO on, maximum fsys External Clock, maximum fsys LPSTOP, VCO off VDD powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation Rating Symbol VDD TA IDD VDDSYN Value 5.0 25 116 500 3 5.0 1.0 4.0 125 60 3.0 7.0 40.0 600 Unit V C mA A A V mA mA A A V A A mW
3
4
5
IDDSYN
6 7 8
VSB ISB PD
Table 75 Thermal Characteristics
Num Characteristic 1 Thermal Resistance Plastic 120-Pin Surface Mount T J = T A + ( P D x JA ) where: TA JA PD PINT PI/O = Ambient Temperature, C = Package Thermal Resistance, Junction-to-Ambient, C/W = PINT + PI/O = IDD x VDD, Watts -- Chip Internal Power = Power Dissipation on Input and Output Pins -- User Determined Symbol JA Value 61.2 Unit C/W
The average chip-junction temperature (TJ) in C can be obtained from: (1)
For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: (2) P D = K / ( T J + 273C ) Solving equations 1 and 2 for K gives: K = P D + ( T A + 273C ) + JA x P 2 D (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
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Table 76 Clock Control Timing (VDD and VDDSYN = 5.0 Vdc 10 %, VSS = 0 Vdc, TA = TL to TH)
Num 1 2 Characteristic PLL Reference Frequency Range1 Symbol fref fsys tlpll fVCO flimp Min 3.2 dc 4(fref) /128 dc -- -- -- -- Max 4.2 16.78 16.78 16.78 20 2 (fsys max) fsys max/2 fsys max 0.5 0.05 % Unit MHz MHz ms MHz MHz
System Frequency2 On-Chip PLL System Frequency Range External Clock Operation PLL Lock Time1, 3, 4, 5, 6 VCO Frequency7 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1
3 4 5
6
CLKOUT Jitter1, 4, 5, 6, 8 Short term (5 s interval) Long term (500 s interval)
Jclk
- 0.5 - 0.05
1. Tested with a 4.194 MHz reference. 2. All internal registers retain data at 0 Hz. 3. Assumes that stable VDDSYN is applied, and that the crystal oscillator is stable. Lock time is measured from the time VDD and VDDSYN are valid until RESET is released. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP. 4. This parameter is periodically sampled rather than 100% tested. 5. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total external resistance from the XFC pin due to external leakage must be greater than 15 M to guarantee this specification. Filter network geometry can vary depending upon operating environment. 6. Proper layout procedures must be followed to achieve specifications. 7. Internal VCO frequency (fVCO ) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and fsys = fVCO / 4. When X = 1, the divider is disabled, and fsys = fVCO / 2. X must equal one when operating at maximum specified fsys. 8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator frequency increase the Jclk percentage for a given interval. When clock jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system.
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Table 77 DC Characteristics (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)
Num 1 Input High Voltage 2 3 4 5 Input Low Voltage Input Hysteresis
1, 2
Characteristic
Symbol VIH VIL VHYS
Min
Max
Unit V V V A A
0.7 (VDD) VDD + 0.3 VSS - 0.3 0.2 (VDD) 0.5 -2.5 -- 2.5
Input Leakage Vin = VDD or VSS
Current3 All input-only pins except ADC pins
IIN
High Impedance (Off-State)3 Leakage Current Vin = VDD or VSS
All input/output and output pins
IOZ
-2.5
2.5
6 7 8 9
CMOS Output High Voltage3, 4 Group 1, 2, 4 input/output and all output pins IOH = -10.0 A CMOS Output Low Voltage3 IOL = 10.0 A Output High Voltage3, 4 IOH = -0.8 mA Group 1, 2, 4 input/output and all output pins Group 1, 2, 4 input/output and all output pins
VOH VOL VOH
VDD -0.2 -- VDD -0.8
-- 0.2 --
V V V
Output Low Voltage3 IOL = 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0 IOL = 5.3 mA Group 2 and Group 4 I/O Pins, BG/CSM IOL = 12 mA Group 3 Data Bus Mode Select5 Pull-up Current Vin = VIL Vin = VIH VDD Supply Current6 Run7 LPSTOP, 4.194 MHz crystal, VCO Off (STSIM = 0) LPSTOP, External clock input frequency = maximum fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current6 4.194 MHz crystal, VCO on, maximum fsys External Clock, maximum fsys LPSTOP, 4.194 MHz crystal, VCO off (STSIM = 0) 4.194 MHz crystal, VDD powered down RAM Standby Voltage8 Specified VDD applied VDD = VSS RAM Standby Current6 Normal RAM operation9 Transient condition Standby operation8 Power Dissipation10 Input Capacitance
2, 3
VOL
-- -- --
0.4 0.4 0.4
V
10
DATA[15:0] DATA[15:0]
IMSP
-- -15
-120 --
A
11
IDD
-- -- -- 4.5
150 2 10 5.5
mA mA mA V
12 13
VDDSYN
IDDSYN
-- -- -- --
2 7 2 2
mA mA mA mA
14
VSB
0.0 3.0 -- -- -- -- -- --
5.5 5.5 50 3 100 865 10 20
V
15
VDD > VSB - 0.5 V VSB - 0.5 V VDD VSS + 0.5 V VDD < VSS + 0.5 V All input-only pins except ADC pins All input/output pins
ISB PD CIN
A mA A mW pF
16 17
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Table 77 DC Characteristics (Continued) (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)
Num Characteristic 18 Load Capacitance3 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0 Group 2 I/O Pins and BG/CSM Group 3 I/O Pins Group 4 I/O Pins Symbol Min -- -- -- -- Max 90 100 130 200 Unit
CL
pF
1. Applies to : Port ADA[5:0] -- AN[5:0] Port E[7:4], 1 -- SIZ[1:0], AS, DS Port F[7:6], 0 -- IRQ[7:6], MODCLK Port GP[7:0] -- IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1 Port QS[7:0] -- TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC EXTAL (when PLL enabled) 2. This parameter is periodically sampled rather than 100% tested. 3. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD Output-Only Pins: ADDR[2:0], BG/CSM, CLKOUT, FREEZE/QUOT, DSO/IPIPE0, PWMA, PWMB Group 1: Port GP[7:0] -- IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1 DATA[15:0], DSI/IPIPE1 Group 2: Port C[3:0] -- ADDR19/CS6, FC[2:0]/CS5/CS3 Port E[7:4], 1 -- SIZ[1:0], AS, DS, DSACK1 Port F[7:6], 0 -- IRQ[7:6], MODCLK Port QS[7:3] -- TXD, PCS[3:1], PCS0/SS ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BG/CSM, BGACK/CSE 4. Does not apply to RESET because it is an open drain pin. Does not apply to Port QS[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 5. Use of an active pulldown device is recommended. 6. Total operating current is the sum of the appropriate IDD, IDDSYN, and ISB values, plus IDDA. IDD values include supply currents for device modules powered by VDDE and VDDI pins. 7. Current measured at maximum system clock frequency, all modules active. 8. The SRAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5 volts. The SRAM array cannot be accessed while the module is in standby mode. 9. When VSB is more than 0.3 V greater than VDD, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum transient condition specification. System noise on the VDD and VSTBY pin can contribute to this condition. 10. Power dissipation is measured at maximum system clock frequency, all modules active. Power dissipation can be calculated using the following expression: PD = Maximum VDD (IDD + IDDSYN + ISB) + Maximum VDDA (IDDA) IDD includes supply currents for all device modules powered by VDDE and VDDI pins.
MOTOROLA 144
MC68HC916X1 MC68HC916X1TS/D
Table 78 AC Timing (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)1
Num Characteristic F1 Frequency of Operation2 1 1A 1B 2, 3 Clock Period ECLK Period External Clock Input Period3 Clock Pulse Width Symbol f tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tAVSA tCLSN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI tCLDI tCLDH Min 4 f(ref)/128 59.6 476 59.6 28 236 29.8 -- -- -- 0 0 0 2 -15 15 2 15 100 45 40 40 -- 15 0 0 15 70 -- 15 15 15 5 20 0 0 -- 15 -- Max 16.78 -- -- -- -- -- -- 5 8 5 29 59 -- 25 15 -- 29 -- -- -- -- -- 59 -- 29 29 -- -- 29 -- -- -- -- -- 80 -- 55 -- 90 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time3 4, 5 CLKOUT Rise and Fall Time 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) 4B, 5B External Clock Input Rise and Fall Time4 6 7 8 9 9A 11 12 13 14 14A 14B 15 16 17 18 20 21 22 23 24 25 26 27 27A 28 29 29A 30 30A Clock High to ADDR, FC, SIZE Valid Clock High to ADDR, Data, FC, SIZE, High Impedance Clock High to ADDR, FC, SIZE, Invalid Clock Low to AS, DS, CS Asserted AS to DS or CS Asserted (Read)5 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated6 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup) Late BERR Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK1, BERR, Negated DS, CS Negated to Data In Invalid (Data In DS, CS Negated to Data In High Hold)7 Impedance7, 8
CLKOUT Low to Data In Invalid (Fast Cycle Hold)7 CLKOUT Low to Data In High Impedance7
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 145
Table 78 AC Timing (Continued) (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)1
Num 31 33 35 37 39 39A 46 46A 47A 47B 48 53 54 55 70 71 72 73 74 75 76 77 78 100 101 102 103 104 105 Characteristic DSACK1 Asserted to Data In Valid9 Clock Low to BG Asserted/Negated BR Asserted to BG Asserted10 Symbol tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA tRWAS tAIST tAIHT tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH tRSTA tRSTR Asserted14
14
Min -- -- 1 1 2 1 150 90 5 15 -- 0 -- 40 0 15 10 15 10 20 0 4 -- 3 3 10 10 10 10
Max 50 29 -- 2 -- -- -- -- -- -- 30 -- 28 -- 29 -- -- -- -- -- -- -- 10 40 40 -- -- -- --
Unit ns ns tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns tcyc tcyc ns ns ns ns ns ns
BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK1, BERR Asynchronous Input Hold Time DSACK1 Asserted to BERR Asserted11 Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time (DATA[15:0], MODCLK, BKPT) Mode Select Hold Time (DATA[15:0], MODCLK, BKPT) RESET Assertion RESET Rise Time12 Time13
CLKOUT High to Phase 1
tCHP1A tCHP2A tP1VSA tP2VSN tSAP1N tSNP2N
CLKOUT High to Phase 2 Asserted
Phase 1 Valid to AS or DS Asserted14 Phase 2 Valid to AS or DS Asserted14 AS or DS Valid to Phase 1 Negated14 AS or DS Negated to Phase 2 Negated14
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. The base configuration of the MC68HC916X1 requires a 4.194 MHz crystal reference. 3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL / (50% - external clock input duty cycle tolerance). 4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
MOTOROLA 146
MC68HC916X1 MC68HC916X1TS/D
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. 6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles. 7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time. 8. Maximum value is equal to (tcyc / 2) + 25 ns. 9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK1 low to data setup time (specification 31) and DSACK1 low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle. 10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles of the current operand transfer are complete. 11. In the absence of DSACK1, BERR is an asynchronous input using the asynchronous setup time (specification 47A). 12. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the SIM drives RESET low for 512 tcyc. 13. External logic must pull RESET high during this period in order for normal MCU operation to begin. 14. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases. 15. Address access time = (2.5 + WS) tcyc - tCHAV - tDICL Chip select access time = (2 + WS) tcyc - tCLSA - tDICL Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = -1.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 147
1 4 CLKOUT 5 NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD 2 3
16 CLKOUT TIM
Figure 24 CLKOUT Output Timing Diagram
1B 4B EXTAL 5B 2B 3B
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD PULSE WIDTH SHOWN WITH RESPECT TO 50% VDD
16 EXT CLK INPUT TIM
Figure 25 External Clock Input Timing Diagram
1A 4A ECLK 5A 2A 3A
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD
16 ECLK OUTPUT TIM
Figure 26 ECLK Output Timing Diagram
MOTOROLA 148
MC68HC916X1 MC68HC916X1TS/D
S0 CLKOUT 6 ADDR[23:0]
S1
S2
S3
S4
S5
8
FC[2:0]
SIZ[1:0] 11 AS 14 15 13
9
DS
9A
12 17
CS 18 R/W 21
20
46
DSACK0* 47A DSACK1 31 DATA[15:0] 27 BERR 48 HALT* 27A 29A 29 28
BKPT 47A ASYNCHRONOUS INPUTS IPIPE0 IPIPE1 100 PHASE 1 102 104 101 PHASE 2 103 105 47B
* ON THE MC68HC916X1, THE HALT AND DSACK0 PINS ARE NOT BONDED AND ARE INTERNALLY PULLED UP TO VDD.
916X1 RD CYC TIM
Figure 27 Read Cycle Timing Diagram
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 149
S0 CLKOUT 6 ADDR[23:20]
S1
S2
S3
S4
S5
8
FC[2:0]
SIZ[1:0] 11 AS 14 15 13
9 21
DS
9
12
CS 20 R/W 46 DSACK0* 47A DSACK1 55 DATA[15:0] 23 BERR 26 54 25 28 22 14A 17
53 48 27A 74
HALT*
BKPT IPIPE0 IPIPE1 100 PHASE 1 102 104 103 101 PHASE 2
73
105
* ON THE MC68HC916X1, THE HALT AND DSACK0 PINS ARE NOT BONDED AND ARE INTERNALLY PULLED UP TO VDD.
916X1 WR CYC TIM
Figure 28 Write Cycle Timing Diagram
MOTOROLA 150
MC68HC916X1 MC68HC916X1TS/D
S0 CLKOUT 6 ADDR[23:0]
S1
S4
S5
S0
8
FC[2:0]
SIZ[1:0] 14B AS 9 12
DS CS 18 R/W 27 46A 30 30A DATA[15:0] 73 29A 29
20
BKPT 100 PHASE 1 102 104 103 101 74 PHASE 2 105
16 FAST RD CYC TIM
IPIPE0 IPIPE1
Figure 29 Fast Termination Read Cycle Timing Diagram
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 151
S0 CLKOUT 6 ADDR[23:0]
S1
S4
S5
S0
8
FC[1:0]
SIZ[1:0] 14B AS DS 9 12
CS 20 R/W 23 DATA[15:0] 73 BKPT IPIPE0 IPIPE1 100 PHASE 1 102 104 101 105 PHASE 2 103
16 FAST WR CYC TIM
46A
24
18
25
Figure 30 Fast Termination Write Cycle Timing Diagram
MOTOROLA 152
MC68HC916X1 MC68HC916X1TS/D
CLKOUT
S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
ADDR[23:0] 7 DATA[15:0]
AS 16 DS
R/W
DSACK0*
DSACK1 47A BR 35 BG 33 BGACK IPIPE0 IPIPE1 100 PHASE 1 102 104 101 PHASE 2 103 105 37 33 39A
* ON THE MC68HC916X1 THE DSACK0 PIN IS NOT BONDED AND IS INTERNALLY PULLED UP TO VDD.
916X1 BUS ARB TIM
Figure 31 Bus Arbitration Timing Diagram -- Active Bus Case
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 153
A0 CLKOUT
A5
A5
A2
A3
A0
ADDR[23:0]
DATA[15:0]
AS 47A BR 35 BG 33 BGACK 33 37 47A
47A
16 BUS ARB TIM IDLE
Figure 32 Bus Arbitration Timing Diagram -- Idle Bus Case
MOTOROLA 154
MC68HC916X1 MC68HC916X1TS/D
S0 CLKOUT 6 ADDR[23:0] 18 R/W 20 AS 9
S41
S42
S43
S0
S1
S2
8
12
15
DS 70 73
71
72
DATA[15:0]
74
BKPT IPIPE0 IPIPE1
100
101 PHASE 1 102 104 103 PHASE 2 105 START OF EXTERNAL CYCLE PHASE 1 PHASE 2
SHOW CYCLE
NOTE: SHOW CYCLES CAN STRETCH DURING CLOCK PHASE S42 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT-STATE INSERTION.
16 SHW CYC TIM
Figure 33 Show Cycle Timing Diagram
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 155
S0 CLKOUT 6 ADDR[23:0]
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
6
8
FC[2:0]
SIZ[1:0] 11 AS 9 DS 12 CS 18 R/W 46 17 9 9 12 14 11 14 13 15
21
17
20 46 29 55
14A
18
25
DATA[15:0] 27 29A 23 53 54
16 CHIP SEL TIM
Figure 34 Chip Select Timing Diagram
77 RESET 75 DATA[15:0], MODCLK, BKPT
78
76
16 RST/MODE SEL TIM
Figure 35 Reset and Mode Select Timing Diagram
MOTOROLA 156
MC68HC916X1 MC68HC916X1TS/D
Table 79 Background Debugging Mode Timing (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)1
Num B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Characteristic DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle Time CLKOUT Low to FREEZE Asserted/Negated CLKOUT High to IPIPE1 High Impedance CLKOUT High to IPIPE1 Valid DSCLK Low Time IPIPE1 High Impedance to FREEZE Asserted FREEZE Negated to IPIPE[1:0] Active Symbol tDSISU tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZAN tIFZ tIF tDSCLO tIPFA tFRIP Min 15 10 15 10 -- 2 -- -- -- 1 TBD TBD Max -- -- -- -- 25 -- 50 50 50 -- -- -- Unit ns ns ns ns ns tcyc ns ns ns tcyc tcyc tcyc
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
CLKOUT
FREEZE B2 BKPT/DSCLK
B3
B9 B0 IPIPE1/DSI B4 IPIPE0/DSO B1 B5
16 BDM SER COM TIM
Figure 36 Background Debugging Mode Timing Diagram -- Serial Communication
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 157
CLKOUT B6 B6
FREEZE
B7 IPIPE1/DSI
B10 B8
B11
16 BDM FRZ TIM
Figure 37 Background Debugging Mode Timing Diagram -- Freeze Assertion
Table 80 ECLK Bus Timing (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)1
Num E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 Characteristic ECLK Low to Address Valid2 ECLK Low to Address Hold ECLK Low to CS Valid (CS Delay) ECLK Low to CS Hold CS Negated Width Read Data Setup Time Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold (Read) CS Negated to Data High Impedance ECLK Low to Data Valid (Write) ECLK Low to Data Hold (Write) CS Negated to Data Hold (Write) Address Access Time (Read)
3
Symbol tEAD tEAH tECSD tECSH tECSN tEDSR tEDHR tEDHZ tECDH tECDZ tEDDW tEDHW tECHW tEACC tEACS tEAS
Min -- 15 -- 15 30 30 5 -- 0 -- -- 15 0 386 296 --
Max 60 -- 150 -- -- -- -- 60 -- 1 2 -- -- -- -- 1/2
Unit ns ns ns ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc
Chip-Select Access Time (Read)4 Address Setup Time
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low. 3. Address access time = tEcyc - tEAD - tEDSR. 4. Chip-select access time = tEcyc - tECSD - tEDSR.
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MC68HC916X1 MC68HC916X1TS/D
CLKOUT 2A ECLK 1A R/W E1 ADDR[23:0] E3 CS E14 E6 E13 READ E7 E11 DATA[15:0] WRITE E12 E9 WRITE E4 E5 E2 3A
E15
DATA[15:0]
E8
E10
HC16 E CYCLE TIM
Figure 38 ECLK Timing Diagram
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 159
Table 81 QSPI Timing (VDD and VDDSYN = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH 200 pF load on all QSPI pins)1
Num Function 0 Operating Frequency Master Slave 1 Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave2 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input3 Output Symbol fop Min DC DC 4 4 2 2 -- 2 2 tcyc - 60 2 tcyc - n 17 13 30 20 0 20 -- -- -- -- 0 0 -- -- -- -- Max 1/4 1/4 510 -- 128 -- 1/2 -- 255 tcyc -- 8192 -- -- -- -- -- 1 2 50 50 -- -- 2 30 2 30 Unit System Clock Frequency System Clock Frequency tcyc tcyc tcyc tcyc SCK tcyc ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns ns ns ns s ns s ns
tqcyc
2
tlead
3
tlag
4
tsw
5
ttd
6
tsu
7
thi ta tdis tv
8 9 10
11
tho
12
tri tro tfi tfo
13
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. For high time, n = External SCK rise time; for low time, n = External SCK fall time. 3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sources are at valid VOH/VOL prior to SCK transitioning between valid VOL and VOH. Due to process variation, logic decision point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used.
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MC68HC916X1 MC68HC916X1TS/D
3 PCS[3:0] OUTPUT 13 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 1 5 12
2
6 7
4
12
13
MISO INPUT
MSB IN 11
DATA
LSB IN
MSB IN
10 DATA LSB OUT PORT DATA 12 MSB OUT
MOSI OUTPUT
PD 13
MSB OUT
16 QSPI MAST CPHA0
Figure 39 QSPI Timing -- Master, CPHA = 0
3 PCS[3:0] OUTPUT 13 5 12
2
SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT
1
1
7
4
12
13 6
MISO INPUT
MSB IN 11
DATA
LSB IN
MSB
10 DATA LSB OUT PORT DATA 12 MSB
MOSI OUTPUT
PORT DATA 13
MSB OUT
16 QSPI MAST CPHA1
Figure 40 QSPI Timing -- Master, CPHA = 1
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 161
3 SS INPUT 13 SCK CPOL=0 INPUT 4 SCK CPOL=1 INPUT 4 8 MISO OUTPUT MSB OUT 7 DATA LSB IN 11 DATA 1 12
2
5
12 10
13
11 PD 13
9 MSB OUT
LSB OUT
6 MOSI INPUT MSB IN
MSB IN
16 QSPI SLV CPHA0
Figure 41 QSPI Timing -- Slave, CPHA = 0
SS INPUT 1 SCK CPOL=0 INPUT 2 SCK CPOL=1 INPUT 10 13 10 DATA 7 DATA 11 SLAVE LSB OUT 12 4 12 13
5
4
3
12 9 PD
8 MISO OUTPUT PD
MSB OUT
6 MOSI INPUT MSB IN
LSB IN
16 QSPI SLV CPHA1
Figure 42 QSPI Timing -- Slave, CPHA = 1
MOTOROLA 162
MC68HC916X1 MC68HC916X1TS/D
Table 82 ADC Maximum Ratings
Num 1 2 3 4 5 6 7 8 9 10 11 12 Analog Supply Internal Digital Supply, with reference to VSSI Reference Supply, with reference to VSSI VSS Differential Voltage VDD Differential Voltage VREF Differential Voltage VRH to VDDA Differential Voltage VRL to VSSA Differential Voltage Disruptive Input Current1, 2, 3, 4, 5, 6, 7 VNEGCLAMP -0.3V VPOSCLAMP 8 V Positive Overvoltage Current Coupling Ratio1, 5, 6, 8 Negative Overvoltage Current Coupling Ratio1, 5, 6, 8 Maximum Input Current 3, 4, 6 VNEGCLAMP -0.3 V VPOSCLAMP 8 V Parameter Symbol VDDA VDDI VRH, VRL VSSI - VSSA VDDI - VDDA VRH - VRL VRH - VDDA VRL - VSSA INA KP KN IMA Min - 0.3 - 0.3 - 0.3 - 0.1 - 6.5 - 6.5 - 6.5 - 6.5 - 500 2000 500 - 25 Max 6.5 6.5 6.5 0.1 6.5 6.5 6.5 6.5 500 -- -- 25 Unit V V V V V V V V A -- -- mA
1. Below disruptive current conditions, a stressed channel will store the maximum conversion value for analog inputs greater than VRH and the minimum conversion value for inputs less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions 2. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals also interfere with conversion of other channels. 3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 4. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using positive and negative clamp values, then use the larger of the calculated values. 5. This parameter is periodically sampled rather than 100% tested. 6. Applies to single pin only. 7. The values of external system components can change the maximum input current value, and affect operation. A voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these adjacent pins. The actual maximum may need to be determined by testing the complete design. 8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an external series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these adjacent pins.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 163
Table 83 ADC DC Electrical Characteristics (Operating) (VSS = 0 Vdc, ADCLK = 2.1 MHz, TA = TL to TH)
Num Parameter 1 Analog Supply1 2 3 4 5 6 7 8 9 10 11 Internal Digital Supply1 VSS Differential Voltage VDD Differential Voltage Reference Voltage Low2, 3 Symbol VDDA VDDI VSSI - VSSA VDDI - VDDA VRL VRH VRH - VRL VINDC VIH VIL IDDA IREF IOFF CINN CINS Min 4.5 4.5 - 1.0 - 1.0 VSSA VDDA / 2 4.5 VSSA 0.7 (VDDA) VSSA - 0.3 -- -- -- -- -- -- Max 5.5 5.5 1.0 1.0 VDDA / 2 VDDA 5.5 VDDA VDDA + 0.3 0.2 (VDDA) 1.0 200 250 150 10 15 Unit V V mV V V V V V V V mA A A nA pF pF
Reference Voltage High2, 3 VREF Differential Voltage3 Input Voltage2 Input High, Port ADA Input Low, Port ADA Analog Supply Current Normal Operation4 Low-Power Stop Reference Supply Current Input Current, Off Channel5 Total Input Capacitance, Not Sampling Total Input Capacitance, Sampling
12 13 14 15
1. Refers to operation over full temperature and frequency range. 2. To obtain full-scale, full-range results, VSSA VRL VINDC VRH VDDA. 3. Accuracy tested and guaranteed at VRH - VRL 5.0 V 10%. 4. Current measured at maximum system clock frequency with ADC active. 5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10 C decrease from maximum temperature.
Table 84 ADC AC Characteristics (Operating)
Num Parameter 1 ADC Clock Frequency 2 8-bit Conversion Time fADCLK = 1.0 MHz fADCLK = 2.1 MHz
1
Symbol fADCLK tCONV
Min 0.5 15.2 7.6 17.1 8.6 --
Max 2.1 --
Unit MHz s
3
10-bit Conversion Time1 fADCLK = 1.0 MHz fADCLK = 2.1 MHz Stop Recovery Time
tCONV tSR
-- 10
s s
4
1. Conversion accuracy varies with fADCLK rate. Reduced conversion accuracy occurs at maximum.
MOTOROLA 164
MC68HC916X1 MC68HC916X1TS/D
Table 85 ADC Conversion Characteristics (Operating) (VDD and VDDA = 5.0 Vdc 5%, VSS = 0 Vdc, TA = TL to TH, 0.5 MHz fADCLK 1.0 MHz, 2 Clock Input Sample Time)
Num Parameter 1 8-bit Resolution1 2 3 4 5 6 7 8 9 8-bit Differential Nonlinearity 8-bit Integral Nonlinearity 8-bit Absolute Error 10-bit Resolution1 10-bit Differential Nonlinearity3 10-bit Integral Nonlinearity 10-bit Absolute Error3,4 Source Impedance at Input5
3 2
Symbol 1 Count DNL INL AE 1 Count DNL INL AE RS
Min -- -0.5 -1 -1 -- -0.5 -2.0 -2.5 --
Typ 20 -- -- -- 5 -- -- -- 20
Max -- -0.5 1 1 -- -0.5 2.0 2.5 --
Unit mV Counts Counts Counts mV Counts Counts Counts k
1. At VRH - VRL= 5.12 V, one 10-bit count = 5 mV and one 8-bit count = 20 mV. 2. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2 count (10 mV) circuit (differential, integral, and offset) error. 3. Conversion accuracy varies with fADCLK rate. Reduced conversion accuracy occurs at maximum fADCLK. Assumes that minimum sample time (2 ADC Clocks) is selected. 4. 10-bit absolute error of 2.5 counts (12.5 mV) includes 1/2 count (2.5 mV) inherent quantization error and 2 counts (10 mV) circuit (differential, integral, and offset) error. 5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result value due to junction leakage is expressed in voltage (VERRJ): VERRJ = RS X IOFF where IOFF is a function of operating temperature, as shown in Table 83. Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the decoupling capacitor used. Error levels are best determined empirically. In general, continuous conversion of the same channel may not be compatible with high source impedance.
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 165
BO UN DA RY
AB SO L
UT E
ER RO R
IDEAL TRANSFER CURVE 8-BIT TRANSFER CURVE (NO CIRCUIT ERROR)
DIGITAL OUTPUT
mV
8-
BI T
A
BO UN DA RY
+2 0
0
20
-2
0m
V
8-
BI T
AB SO L
UT E
INPUT IN mV, VRH - VRL = 5.120 V
40
ER RO R
B
C
60
A - +1/2 COUNT (10 mV) INHERENT QUANTIZATION ERROR B - CIRCUIT-CONTRIBUTED +10mV ERROR C - + 20 mV ABSOLUTE ERROR (ONE 8-BIT COUNT)
ADC 8-BIT ACCURACY
Figure 43 8-Bit ADC Conversion Accuracy
MOTOROLA 166
MC68HC916X1 MC68HC916X1TS/D
BO UN DA RY
ER RO R
IDEAL TRANSFER CURVE
DIGITAL OUTPUT
AB SO L
C
BO UN DA RY
10-BIT TRANSFER CURVE
(NO CIRCUIT ERROR)
mV
+1 2
.5
10
-B IT
0
20
-1
2.5
mV
10
-B IT
AB SO L
UT E
A
INPUT IN mV, VRH - VRL = 5.120 V
40
ER RO R
B
UT E
60
A - +.5 COUNT (2.5 mV) INHERENT QUANTIZATION ERROR B - CIRCUIT-CONTRIBUTED +10 mV ERROR C - +12.5 mV ABSOLUTE ERROR (2.5 10-BIT COUNTS)
ADC 10-BIT ACCURACY
Figure 44 10-Bit ADC Conversion Accuracy
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 167
Table 86 BEFLASH/Flash EEPROM Module Specifications
Num 1 Characteristic Program/Erase Supply Read Operation Program/Erase/Verify Operation Program/Erase Supply Current2 Read Operation Program/Erase/Verify Operation Verify (ENPE = 0) Program Byte (ENPE = 1) Program Word (ENPE = 1) Erase (ENPE = 1) Program Recovery Time Program Pulse Width Number of Program Program Margin4 Pulses3 Voltage1 Symbol VFPE Min VDD - 0.5 11.4 -- IFPE -- -- -- -- -- 20 -- 100 -- -- 90 -- Max 5.5 12.6 15 50 15 30 4 3 25 50 -- 5 tei x k 110 nep tei x k k=1 -- -- Unit V A A mA mA mA cycles A -- % -- ms ms ms ms A
2
3 4 5 6 7 8 9 10 11 12
tpr pwpp npp pm nep tepk tei em
Number of Erase Pulses3 Erase Pulse Time Amount to Increment tep Erase Margin
Erase Recovery Time Low-Power Stop Recovery Time5
ter tsb
1 1
1. VFPE must not be raised to programming voltage while VDD is below specified minimum value. VFPE must not be reduced below minimum specified value while VDD is applied. 2. Current parameters apply to each individual EEPROM module. 3. Without margin. 4. At 100% margin, the number of margin pulses required is the same as the number of pulses used to program the byte or word. 5. Parameter measured from end of write cycle that clears STOP bit in FEEMCR.
Table 87 BEFLASH/Flash EEPROM Module Life
Num 1 2 Data Retention Parameter Program-Erase Endurance1
2
Symbol epe rd
Value 100 10
Unit cyc yr
1. Number of program-erase cycles (1 to 0, 0 to 1) per bit. 2. Parameter based on accelerated-life testing with standard test pattern.
MOTOROLA 168
MC68HC916X1 MC68HC916X1TS/D
13.5 V 12.6 V 11.4 V
30 ns MAXIMUM VFPE ENVELOPE VDD ENVELOPE COMBINED VDD AND VFPE
6.5 V 4.5 V 4.0 V
- 0.30 V
0V POWER ON NORMAL READ PROGRAM ERASE VERIFY POWER DOWN
PROG VOLT ENVELOPE
Figure 45 Programming Voltage Envelope
PROGRAMMING VOLTAGE POWER SUPPLY
D1 R1 10 k VFPE PIN
VDD
4.5 V
D2
R2 22 k
C1 0.1 F
VFPE CIRCUIT
Figure 46 VFPE Conditioning Circuit
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 169
NOTES
MOTOROLA 170
MC68HC916X1 MC68HC916X1TS/D
NOTES
MC68HC916X1 MC68HC916X1TS/D
MOTOROLA 171
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and B are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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